在多重處理器系統晶片中，使用多個處理器平行處理以提升總體的效能，然而處理器之間通訊以及記憶體存取的效能會顯著的影響總體效能。我們提出了一種用於系統合成的通訊效能估測的軟體設計，主要針對多處理器系統晶片網狀通訊結構設計硬體模擬器。我們將路由節點的模擬，以SystemC程式語言來實現，再使用通訊模擬量測數據訓練通訊效能分析模型，可以估測多處理器系統晶片上處理器之間的通訊效能。

In a multiprocessor system-on-chip (MPSOC), parallel processors are utilized to enhance overall performance. However, the communication between processors and memory modules can affect overall performance significantly. We proposed a software design of communication performance estimation for system synthesis. We designed a hardware simulator of mesh communication architecture of MPSOC. We implemented the simulator of router nodes in SystemC language. An analytical communication performance estimation model can be trained with data measured from communication simulation. It can then be utilized for estimating inter-processor communication performance in an MPSOC.

第一章 導論...............................................................1
1.1 研究動機......................................................................1
1.2 研究背景......................................................................3
1.3 研究目的......................................................................4
1.4 論文架構......................................................................5
第二章 系統合成的通訊效能估測...........................6
2.1 多重處理器系統晶片結構..........................................6
2.2 系統合成的通訊效能估測的設計流程與方法..........7
2.3 路由節點的規劃與設計..............................................9
2.3.1傳送的訊息資料........................................................9
2.3.2輸入模組的設計......................................................10
2.3.3輸出模組的設計......................................................14
2.4維度優先路由演算法..................................................15
2.5模擬模型......................................................................17
第三章 軟體設計與實驗規劃..................................21
3.1模擬模型的軟體設計系統流程..................................21
3.2 SystemC軟體介紹....................................................22
3.3實驗評量方法的規劃..................................................24
第四章 結論..............................................................25
第五章 參考文獻......................................................26

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[2] T. Lee & J. D. Jian, “Software Design of a Task-level High Level Synthesis Method,” Tech. Rep.CAD-04-03,Dept. of Electrical Engineering, National Sun Yat-Sen University, Kao-Hsiung, Taiwan, 2004

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[5] J.Cong,Z.Zhang, “An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation,” Proceedings of the 43rd annual conference on Design automation,pp.433 – 438, 2006

[6] C. J. Beckmann,C. D. Polychronopoulos, “Microarchitecture Support for Dynamic Scheduling of Acyclic Task Graphs,” Proceedings of the 25th annual international symposium on Microarchitecture,pp. 140-148, 1992
[7] Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen, “A Virtual Channel Router for On-chip Networks,” IEEE Int. SOC Conf., Santa Clara, California. pp. 289-293, 2004

[8] 國家晶片系統設計中心 — SystemC語言概論