Responsive image
博碩士論文 etd-0401108-174734 詳細資訊
Title page for etd-0401108-174734
論文名稱
Title
ARM10-like微處理器之設計與實作
Design and Implementation of an ARM10-like Microprocessor
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
167
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2008-01-14
繳交日期
Date of Submission
2008-04-01
關鍵字
Keywords
微處理器、管線式架構、晶片系統整合
Microprocessor, Pipeline architecture, SoC intrgration
統計
Statistics
本論文已被瀏覽 5668 次,被下載 0
The thesis/dissertation has been browsed 5668 times, has been downloaded 0 times.
中文摘要
ARM是目前市面上被應用的最廣泛的中央處理單元之一,它擁有高效能、低成本和低耗電量等特色。本論文主要的目的是設計並且實作一顆仿ARM10的微處理器SYS32TME-III,以ARM公司的32位元精簡指令集架構微處理器ARM10的架構為主,從設計的過程以及實作的角度進而描述其基於暫存器轉換層級設計上的衍生架構的特性分析。以時脈速度200MHz為目標來作為設計策略,並將重點放在效能的最佳化部份,使用預先指令提取、分支預測、平行處理、指令執行路徑以及計算單元執行路徑最佳化等機制中加以改良,比較其結果並且探討其設計心得。
Abstract
ARM microprocessor is one of the CPU most extensively applied to electronic products in the market, with the advantages of high efficiency, low power consumption, and low cost. The purpose of this thesis is to design and implement an ARM10-like microprocessor SYS32TME-III, it is based on the frame of 32-bits RISC architecture of ARM10, and to analyze the character of derivative architecture on RTL design with the point of view between the process of the design and implementation. For design strategy, speed 200MHz is the goal, and performance-optimized is the main point. Then, improve the mechanisms of adopting instruction pre-fetch, branch prediction, parallel execution, executive path of instruction and operation unit, and compare its results, probe into what’s learning from the design.
目次 Table of Contents
Chapter 1. Introduction
1. 1 背景
1. 2 動機
1. 3 研究方法
1. 4 主要貢獻
1. 5 論文架構
Chapter 2. Relative Works
2. 1 ARM
2. 1. 1 ARM7TDMI
2. 1. 2 ARM9
2. 1. 3 ARM10
2. 2 SPARC
2. 2. 1 Casablanca II[21]
2. 2. 2 LEON II
Chapter 3. Implementation of Microprocessor
3. 1 訊號描述(Signal Description)
3. 2 管線式架構(Pipeline Architecture)
3. 3 指令提取階段(Fetch Stage)
3. 3. 1 功能元件和資料路徑
3. 3. 2 指令預先提取
3. 3. 3 分支預測
3. 4 指令發布階段(Issue Stage)
3. 4. 1 功能元件和資料路徑
3. 4. 2 指令編碼路徑
3. 4. 3 指令標籤
3. 4. 4 平行處理的執行機制
3. 5 指令解碼階段(Decode Stage)
3. 5. 1 功能元件和資料路徑
3. 5. 2 指令解碼單元
3. 5. 3 暫存器備份還原模組
3. 5. 4 預先運算機制(Pre-calculating function)
3. 5. 5 前饋機制(Forwarding function)
3. 6 指令執行階段(Execute Stage)
3. 6. 1 功能元件和資料路徑
3. 6. 2 條件式執行(Conditional Execution)
3. 6. 3 例外中斷控制元件
3. 7 記憶體存取階段(Memory Access Stage)
3. 7. 1 功能元件和資料路徑
3. 7. 2 Hit under miss功能
3. 7. 3 平行處理的寫入機制
3. 8 資料寫回階段(Write Back Stage)
3. 8. 1 功能元件和資料路徑
3. 9 危障暫停機制(Hazard stall function)
3. 9. 1 系統危障暫停路徑
3. 9. 2 fs-stall暫停機制
3. 9. 3 pa-stall暫停機制
3. 9. 4 int-stall暫停機制
3. 9. 5 pdw-stall暫停機制
3. 9. 6 mlt-stall暫停機制
3. 9. 7 mac-stall暫停機制
3. 9. 8 lsd-stall暫停機制
3. 9. 9 lpm-stall暫停機制
3. 9. 10 HUM-stall(Hit-under-miss stall)暫停機制
3. 10 例外中斷控制機制(Exception & interrupt function)
3. 11 DSP延伸指令集
Chapter 4. Design Architecture Tradeoffs
4. 1 Count leading zeros
4. 1. 1 實作方式一:Rippled CLZ
4. 1. 2 實作方式二:Banked CLZ
4. 2 乘法
4. 2. 1 實作方式一:單一週期乘加器
4. 2. 2 實作方式二:分割加法二週期乘加器
4. 2. 3 實作方式三:分割乘法二週期乘加器
4. 2. 4 實作方式四:三週期乘加器
4. 3 位移器以及ALU運算路徑
4. 3. 1 實作方式一:Designware位移器
4. 3. 2 實作方式二:客製化位移器
4. 3. 3 實作方式三:二週期位移器
Chapter 5. Verification and Synthesis
5. 1 Verification
5. 1. 1 Verification strategy
5. 1. 2 Functional verification
5. 1. 3 Instruction-level verification
5. 1. 4 Instruction cycle times
5. 2 Implement result
5. 2. 1 Synthesis result
5. 2. 2 Synthesis comparison
5. 2. 3 Cost and performance analysis
5. 2. 4 Real case cycle analysis
5. 3 SoC integration
5. 3. 1 系統概述
5. 3. 2 實驗結果
Chapter 6. Conclusion
6. 1 Conslusion
6. 2 Future works
參考文獻
附錄A. ARMv5TE指令集新增指令
附錄B. SYS32TME與SYSTME-III的架構差異
參考文獻 References
[1]ARM7TDMI Processor Family Overview http://www.arm.com/products/CPUs/ARM7TDMI.html
[2]ARM926EJ-S Processor Family Overview http://www.arm.com/products/CPUs/ARM926EJ-S.html
[3]莊偉傑 ”2001年SIP廠商市場佔有率分析”, 工研院IEK電子組, http://www.itri.org.tw/chi/services/ieknews/e0212-B10-00000-AD18-0.doc
[4]賴奇邵 “ARM7微處理器之衍生架構”,國立中山大學嵌入式實驗室,2001年七月
[5]宋裕文 “微處理器硬體架構特色之微架構評估與改善”, 國立中山大學嵌入式實驗室,2003年八月
[6]Ing-Jer Huang, Wen-Kai Huang, Rui-Ting Gu and Chung-Fu Kao, “A Cost Effective Multimedia Extension to ARM7 Microprocessors,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2002, pp. 304-307.
[7]Ing-Jer Huang, Tse-Chen Yeh, “The Design and Implementation of a Multimedia Coprocessor for ARM7 Microprocessors,” in proceedings of the 12th Workshop on Synthesis And System Integration of Mixed Information Technologies, Kanazawa, Japan,2004
[8]丁邦安, 嵌入式微處理器核芯應用系列(二)ARM核芯簡介, IC Design, pp. 38-56, February 2001
[9]Simon Segar, “The ARM9 Family – High Performance Microprocessors for Embedded Applications” IEEE International Conference on Computer Design 1999 (ICCD’99).
[10]Steve Furber “ARM system–on-chip architecture”, second edition, Addison Wesley Longman Inc, 2000.
[11]Michael Keating and Pierre Bricaud “Reuse Methodology Manual for System-on-a-Chip Designs”, 2nd Edition, KLUWER ACADEMIC PUBLISHERS.
[12]David A. Patterson and John L. Hennessy, “Computer Origanization & Design – The Hardware/Software Interface”, 2nd Edition, Margan Kaufmann Publishers, Inc.
[13]John L. Hennessy and David A. Patterson, “Computer Architecture A Quantitative Approach” 3rd Edition, Margan Kaufmann Publishers, Inc.
[14]Behrooz Parhami, “Computer Arithmetic - Algorithms and Hardware Designs”, Oxford University Press, Inc.
[15]Yu-Liang Hung, “Cost-effective Microarchitecture Optimization for ARM7TDMI Microprocessor”, ICS 2000.
[16]L. Gwennap“Intel, HP Make EPIC Disclosure”Microprocessor Report, Oct. 27, 1997, pp.1, 6-9
[17]Richardson, N.; Lun Bin Huang; Hossain, R.; Lewis, J.; Zounes, T. and Soni, N “The iCore 520-MHz synthesisable CPU core”IEEE Micro, May-June 2003
[18]ARM wiki http://zh.wikipedia.org/wiki/ARM%E6%9E%B6%E6%A7%8B
[19]SPARC wiki http://zh.wikipedia.org/w/index.php?title=SPARC&variant=zh-tw
[20]Cadman, R., ” SPARC architecture and processor implementation” IEE Colloquium on ISC Architectures and Applications, 4 Nov 1991
[21]Tanaka, K., “Casablanca II: implementation of a real-time RISC core for embedded systems” ASAP 2005, 23-25 July 2005
[22]Garner, R.B.; Agrawal, A.; Briggs, F.; Brown, E.W.; Hough, D.; Joy, B.; Kleiman, S.; Muchnick, S.; Namjoo, M.; Patterson, D.; Pendleton, J.; Tuck, R. “The scalable processor architecture (SPARC)” Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, March 1988
[23]Product : Leon II http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=12&Itemid=52
[24]Cowell, M.; Postula, A. “Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs” Digital System Design 2006, Oct 2006
[25]Leon wiki http://zh.wikipedia.org/w/index.php?title=LEON&variant=zh-tw
[26]Faraday FA5 Series RISC Processors http://www.faraday-tech.com/html/products/IP/processor/fa500.html
[27]ARM922T Processor Family Overview http://www.arm.com/products/CPUs/ARM922T.html
[28]ARM1022E Processor Family Overview http://www.arm.com/products/CPUs/ARM1022E.html
[29]David Seal, “ARM Architecture Reference Manual” , 2nd Edition,Addison Wesley Longman Inc
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內校外均不公開 not available
開放時間 Available:
校內 Campus:永不公開 not available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 3.81.30.41
論文開放下載的時間是 校外不公開

Your IP address is 3.81.30.41
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code