對於即時系統來說，為了增加其系統的可靠度，短暫性錯誤的偵測及回復則成為一個重要的議題。在過去的所提出的方法中，為了偵測到控制程序錯誤，且回復控制程序錯誤所導致的資料錯誤，會在每個basic block檢查簽章，並設立還原點將資料做一次完整的備份。然而，頻繁的檢查並將資料完整地備份，這會迫使效能下降。另一方面，在發生錯誤後，也需花額外的時間，將系統返回到上一個還原點，並將備份的資料從記憶體中讀出，取代資料錯誤的暫存器。
因此，我們提出了一個新的方法，主要可分為三大方向。第一，透過事前分析，我們只需要針對有比較高機率會發生控制程序錯誤的basic block做關鍵簽章插入法，並設立還原點；第二，在設立還原點並備份暫存器資料時，只備份可能會因為控制程序錯誤而導致資料錯誤的暫存器；第三，當錯誤發生後，且在下次寫入新的值取代資料錯誤的暫存器之前，直接從checkpoint storage中讀取資料來運算。從實驗結果得知，此方法需額外加入的指令數較少而減少記憶體使用率最多可少2.4倍，且因為設立的還原點較少可大幅的提升執行效能最快可達11.9倍，而修正錯誤的所需的時間較短最多可節省20 cycle times，但偵測到的錯誤覆蓋率最差約少1.5%。

For the real-time systems, the error detection and recovery of the transient fault have become an important issue to improve the reliability. In previous works, in order to detect the control flow error, and recovery the data error caused by control flow error (CFE), they will check signatures, and set a checkpoint to make a complete backup of the data in each basic block. However, frequent checks and data backups complete, which can reduce performance. On the other hand, after an error occurs, it’s not necessary to have performance overhead on recovery the data from checkpoint storage to registers.
The proposed technique has three main ideas. First, through sensitivity analysis result, it only does a critical signature assertion for the basic blocks which have a higher probability of the CFE. Second, in checkpoint phase, it only backs up the registers which might have the data corruption for a checkpoint. Third, in the recovery phase, it will read the checkpoint value from checkpoint storage for execution directly. In experiment results, the proposed technique has a significant decrease in memory overhead of additional instruction about 2.4 times and less performance overhead of additional execution about 11.9 times at most. It also shows the difference in error correction latency about 20 cycle times in the best case, but it has lower fault coverage about 1.5%.

論文審定書…………………………………………………………………….i
論文公開授權書 ......................................................................................ii
論文聲明書…………………………………………………………………....iii
致謝……………………………………………………………………………iv
中文摘要………………………………………………………………………vi
Abstract……………………………………………………………………….vii
Table of Contents ................................................................................. viii
List of Figures………………………………………………………………..x
List of Tables………………………………………………………………....xiii
Chapter 1. Introduction………………………………………………...1
1.1 Background..…………………………………………………….........1
1.2 Motivation………………………………………………………………3
1.3 Organization of the Thesis……………………………………………5
Chapter 2. Related Works……………………………………………..6
2.1 Fault Model of Control Flow Errors…………………………………6
2.2 Fault-Tolerant Approaches Overview………………………………7
2.3 Drawback of Previous Works………………………………………11
Chapter 3. Overview of Control Flow Error Recovery Technique..20
3.1 Critical Signature/Checkpoint/Recovery Assertion Technique.....22
3.1.1. Sensitivity Analysis…………………………………………….22
3.1.2. Critical Signature/Checkpoint/Recovery Assigner………….25
3.1.1. Convergence Testing………………………………………….28
3.2 On-the-fly Checkpoint and Recovery Technique…………………30
3.2.1. Performance Issue of Reducing Register Checkpoint and Recovery Policy………………………………………………………………………..30
3.2.2. On-the-fly Hardware Architecture……………………………32
Chapter 4. Experiment and Results………………………………..39
4.1 Experiment Set Up………………………………………………….39
4.2 Experiment Results…………………………………………………43
Chapter 5. Conclusion and Future Work…………………………..57
References………………………………………………………………...60
Appendix A. Critical Signature Assertion with Pure Software-based
Checkpoint and Recovery Technique…………………………………..63
Appendix B. Introduction of an IDE Environment...............................66
Appendix C. Implementation of CEDA…………………………………70

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