近年來主動陣列平面顯示器廣泛的使用在消費性電子產品上，隨著平面顯示器的普及化，市場競爭也更加激烈，對於平面顯示器性能的要求也越來越高，低溫多晶矽(LTPS)由於具有較高的移動率(mobility)以及驅動電流，可將顯示器週邊的電路例如控制器、記憶體等同時製作在低溫多晶矽 (LTPS)玻璃基板上，達到系統整合 (system on panel) 的目的，使得平面顯示器更輕薄，減少可靠度問題，並節省製作成本。在本論文中，我們研究應用於系統面板上的非揮發性記憶體。希望以增加記憶體密度或是減少製程步驟等方式，降低記憶體的單位成本。因此我們提出幾項新穎的記憶體操作方式。
首先我們利用通道熱電子(channel hot electron)寫入方式，將電子注入到SONOS (silicon-oxide-nitride-oxide-silicon)電晶體的源極或汲極端，達到二位元的記憶效果，提升SONOS 電晶體的記憶密度。在本單元中我們發現，以通道熱電子方式寫入SONOS 電晶體後，通道較短的電晶體才有二位元的記憶效果，通道較長的電晶體不具二位元記憶特性，此特性與電子注入到氮化矽層的位置有關。當電子注入到通道上方的氮化矽層會產生額外的能量障礙，使得電晶體的臨界電壓(threshold voltage) 增加，達到寫入的效果。若電子注入到源/汲極端PN接面的空乏區，其產生的能量障礙相較於源極-基底(body)之間的內建電位(Built-in Potential)並不明顯，因此寫入效果不明顯。當電晶體的通道長度短到足以降低源極-基底之間的內建電位大小，寫入的電子在空乏區產生的能量障礙可以影響通道電子，使得電晶體的臨界電壓增加，達到寫入的效果。因此以通道熱電子方式寫入SONOS記憶體，通道較短的電晶體才有二位元的記憶效果。
第二部份，我們將電荷儲存到薄膜電晶體的基底上，使一般的薄膜電晶體變成非揮發性記憶體，此方法不需非揮發性記憶體的浮停閘(floating gate)以及穿遂氧化層等製程，因此可以減少記憶體製作在面板上的成本。在本單元中，我們利用薄膜電晶體的自我加熱(self-heating)現象，在閘極的垂直電場作用下藉由熱場發射(thermion field emission)來產生電子-電洞對，閘極的垂直電場將電子電洞對分離後，將電洞注入並儲存到薄膜電晶體的基底上完成寫入動作，而抹除係利用源/汲極端的橫向電場將基底上的電洞移除。
第三部份，我們利用SONOS記憶體單邊ＦＮ穿遂(Fowler-Nordheim tunneling)，使單一薄膜電晶體除了當畫素開關，同時可當二位元記憶體，在同一記憶胞(cell)上記憶二位元的資料，因此SONOS 電晶體的記憶密度可以增加。電晶體的閘極-汲極重疊部分(overlap)有較大的電場，記憶體在寫入時電子會注入此重疊的區域，並且在汲極區域上方產生額外的偏壓，產生極大的閘極感應汲極漏電流(GIDL)。在本單元中，我們利用通道ＦＮ穿遂將電子注入到SONOS 電晶體的氮化矽層，此時源極與汲極端的GIDL電流增加，完成寫入動作。而抹除動作係利用源/汲極端單邊ＦＮ穿遂將源極或汲極端氮化矽層的電子移除，此時源極或汲極端的GIDL電流減少。而源/汲極端的記憶狀態係由源/汲極端的GIDL電流大小判讀。
第四部份，我們將電荷儲存到SONOS電晶體的源極、通道與汲極上方的氮化矽層，使SONOS電晶體具有三位元的記憶效果，因此SONOS 電晶體的記憶密度可以大幅增加。源/汲極端的寫入與抹除動作係利用通道熱電子與單邊ＦＮ穿遂方式完成，而通道的寫入與抹除動作係利用通道ＦＮ穿遂方式完成。在本單元中，我們利用源/汲極端的GIDL電流大小判讀源/汲極端的記憶狀態，而通道的記憶狀態係利用通道的臨界電壓判讀。
此外若利用上述方式，將N種不同數量的電子儲存在SONOS電晶體的源極、汲極與通道上方的氮化矽層，則可進一步儲存N3種記憶狀態，記憶密度遠超過一般的MLC(multi level cell)快閃記憶體( flash memory)。一般MLC 快閃記憶體係將4種數量的電子儲存在浮停閘，共有四種記憶狀態。若利用本論文方法，將4種數量的電子儲存在SONOS電晶體的源極、汲極與通道上方，則可儲存64種記憶狀態，達到6位元的記憶效果，遠超過一般數位式記憶體的記憶極限(四位元)，記憶密度可以大幅度增加。

Recently, active matrix flat-panel displays are widely used in consumer electronic products. With increasing popularity of flat-panel displays, market competition becomes more intense and demands for high performance flat-panel displays are increasing. Low-temperature polysilicon (LTPS) with higher mobility, as well as drive current can integrate electric circuit, such as controllers and memory on glass substrate of display to achieve the purpose of system on panel (SOP). Thus, flat-panel displays can be more compact, while reducing reliability issues and lowering production costs.
In this dissertation, we studied the nonvolatile memory for system on panel applications and reducing cost of memory by increasing the memory density or reducing the processing steps. Therefore, we proposed several modes of operation in nonvolatile memory.
First, we use channel hot-electron (CHE) to inject electrons into the nitride layer that’s above source or drain sides of SONOS thin film transistor (TFT). Thus, we can increase the memory density by storing two-bit state in a memory cell. In this study, the two-bit memory effect is clearly observed for devices with a shorter gate length after CHE programming; however, the two-bit memory effect is absent in devices with a longer gate length. The gate-length-dependent two-bit memory effect is related to the location of injected electrons in the nitride layer. When electrons are injected into the nitride layer above the channel, they can create an additional energy barrier in the channel thus increasing the threshold voltage of the device to perform the programming operations. However, if electrons are injected into the depletion region at the P-N junction between the drain and the channel, the energy barrier induced by electrons is not significant when exchanging the source and drain electrodes to measure the memory status, and the program effect is not as significant. When the channel length is shorten, the built-in potential between the source and the channel can be decreased, the energy barrier caused by programmed electrons can affect electrons in the channel and increase the threshold voltage. Therefore, the two-bit memory effect can be seen in devices with the shorter gate length after CHE programming.
Secondly, we stored charges in the body of the thin film transistor to make the conventional thin-film transistors become a non-volatile memory. This method does not need a floating gate or a tunneling oxide in the memory cell; therefore the memory cost can be reduced. In this study, we used trap-assisted band-to-band thermionic field emission enhanced by self-heating in TFT to produce electron-hole pairs. The hole will be separated by a vertical field under the gate and be injected into the body of TFT to complete the programming operation. The erasing operation is performed by applying a lateral electric field between the source/drain to remove holes in the body of TFT.
Thirdly, we proposed an edge-FN tunneling method to allow SONOS TFT possess not only a pixel switch but also a two-bit nonvolatile memory function in a display panel, thus causing the memory density to increase. In this study, we used a channel FN tunneling to program the SONOS TFT. Because the electric field in the gate-to-drain overlap region is larger than that in the channel region, it will cause a smoother electron injection into the nitride layer inside of the gate-to-drain overlap region, which also increases the gate-induced drain leakage (GIDL) current. The edge-FN tunneling method is used to erase electrons in the gate-to-drain overlap region, by doing so, the GIDL current has decreased. The memory status at the source/drain side is determined by the corresponding GIDL current of the SONOS TFT.
Fourthly, we stored electrons in the nitride layer at source, channel, and drain regions of SONOS TFT to make sure that TFT possess a three-bit memory effect in a unitary cell, which also allows the memory density to increase significantly. In this study, programming and erasing operations in the source/drain region are performed by channel hot-electron injection and edge-FN tunneling method, while that in the channel region are accomplished by channel FN tunneling. The memory status in the source/drain is determined by the corresponding GIDL current, while that in the channel region by threshold voltage of the device The memory density for the device operated by proposed method can be further increased.
In addition, if we store a number of N different types of electrons in those three regions mentioned above, there are N3 status can be stored in a memory cell. The memory density can beyond conventional multi-level-cell (MLC) flash memory. Two-bit memory effect per cell in a MLC flash memory can be achieved by storing four quantitative electrons in the floating gate of the memory device. If we store four quantitative electrons in the nitride layer at source, channel, and drain regions of SONOS TFT, we can obtain 64 memory states or 6-bit memory effect in a memory cell. Thus, the proposed concept is promising to storage the messages in a memory cell beyond four-bit.

Chinese Abstract……………………………………………...............I
English Abstract……………………………………………….........IV
Acknowledgments………………………………………..IX
Contents…………………………………………………...XI
Figure Captions……………………………………………….....XIV

Chapter 1: Introduction to Nonvolatile Memory
1.1 General Background…..................................1
1.1.1 Overview of Active Matrix Flat-Panel Displays…...1
1.1.2 Overview of Floating Gate Type Nonvolatile Memory…2
1.2 Motivation……………......................................3
1.3 Organization of the Dissertation……….......4

Chapter 2: The Electrical Characteristics of Floating Gate Type Nonvolatile Memory
2.1 Operation Principles of Floating Gate Type Memory Devices……………………………………………………..8
2.2 Programming Operation…………………...9
2.3 Erasing Operation…………………………11
2.4 Reading Operation………………………...11
2.5 Reliability tests for Nonvolatile Memory...12
2.6 Scaling Limitation……………….................13

Chapter 3: Gate-Length-Dependent Two Bit Memory Effect for Pi-Shape Gate Nanowire Polycrystalline Silicon Thin-Film Transistor
3.1 Introduction...................................................23
3.2 Experiment…................................................25
3.3 Results and Discussion……………........26
3.4 Summary.……………………………..........29

Chapter 4: Nonvolatile Memory Device Using Holes Trapped in TFT Active Channel
4.1 Introduction....................................................35
4.2 Experiment
4.2.1 N-channel SONOS TFTs fabrication procedure............................................................................37
4.2.2 N-channel TFTs fabrication procedure…………………................................................37
4.3 Results and Discussion
4.3.1 Unusual Threshold Voltage Shift Caused by Self-Heating Induced Charge Trapping Effect….........38
4.3.2 Nonvolatile Memory Device Using Holes Trapped in TFT Active Channel………………...............41
4.4 Summary.……………………………...........44

Chapter 5: A Two-Bit Nonvolatile Memory Device with a Transistor Switch Function Accomplished with Edge-FN Tunneling Operation
5.1 Introduction....................................................54
5.2 Experiment...…………….............................56
5.3 Results and Discussion………………....58
5.4 Summary.......................................................60

Chapter 6: Three-Bit per Cell Nonvolatile SONOS-TFT Memory Accomplished by Storing Charges in Nitride Layer over Source/Drain/Channel Regions
6.1 Introduction....................................................67
6.2 Experiment……………….............................69
6.3 Results and Discussion……….................69
6.4 Summary…………………………................72

Chapter 7: Conclusion......................................................81
References………………………………………………..83
Biography………………………………….........................98
Publication List…………………………………………......................100

Chapter 1
[1.1] T. C. Lu, H. W. Zan, M. D. Ker, " Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2583-2589, Oct. 2008.
[1.2] Z. Meng, H. Chen, C. Qiu, H. S. Kwok, and M. Wong, “Active-matrix organic light-emitting diode display implemented using metal-induced unilaterally crystallized polycrystalline silicon thin-film transistors,” in SID Tech. Dig., 2001, pp. 380–383.
[1.3] K. Yoneda, R. Yokoyama, and T. Yamada, “Development trends of LTPS TFT LCDs for mobile applications,” in Proc. Symp. VLSI Circuits, pp. 85–90, 2001.
[1.4] S. Nakashi et al., “As low-temperature polySi LCDs appear, hurdles remain,” Display Devices, no. 20, pp. 20–21, Fall 1999.
[1.5] H. Tokioka, M. Agari, M. Inoue, T. Yamamoto, H. Murai, and H. Nagata, “Low power consumption TFT-LCD with dynamic memory embedded in pixels,” in Proc. SID, pp. 280–283, 2001.
[1.6] T. Aoyama, K. Ogawa,Y. Mochizuki, and N.Konishi, “Inverse staggered poly-Si and amorphous Si double structure TFT's for LCD panels with peripheral driver circuits integration,” IEEE Trans. Elec. Dev., 43, pp. 701 (1996)
[1.7] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech, J., 46, 1288 (1967).
[1.8] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[1.9] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[1.10] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge 1-x x”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[1.11] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[1.12] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS”, IEEE circuits & devices, 16, 22 (2000).
[1.13] J. S. Witters, G. Groeseneken and H. E. Maes, “Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits,” IEEE Jounal of Solid State Circuits, pp. 1372 (1989).
[1.14] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. H. Yeh, C. F. Weng, S. M. Sze, C. Y. Chang, C. H. Lien, “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels,” Appl. Phys. Lett. 90, 122111, Mar. 2007
[1.15] A. J. Walker, S. Nallamothu, E.-H. Chen, M. Mahajani, S. B. Herner, M. Clark, J. M. Cleeves, S. V. Dunton, V. L. Eckert, J. Gu, S. Hu, J. Knall,M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, “3D TFT-SONOS memory cell for ultra-high density file storage applications,” in VLSI Symp. Tech. Dig., Jun. 2003, pp. 29–30.

Chapter 2
[2.1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech, J., 46, 1288 (1967).
[2.2] E. Lusky, Y. Shacham-Diamand, G. Mitenberg, A. Shappir, I. Bloom, and B. Eitan, ”Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices,” IEEE Trans. Electron Devices, vol. ED-51, pp. 444–451, Mar. 2004.
[2.3] S. Tam, P.K. Ko and C. Hu, “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s”, IEEE Trans. Electron Devices, 31(9), pp. 1116-1125, 1984.
[2.4] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—An overview,” Proc. IEEE, vol. 85, pp. 1248–1271, Aug. 1997.
[2.5] T. C. Chen, T. C. Chang, F. Y. Jian, S. C. Chen, C. S. Lin, M. H. Lee, J. S. Chen, and C. C. Shih, ” Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device,” IEEE Electron Device Lett., VOL. 30, NO. 8, pp. 834–836, Aug. 2009
[2.6] A. Padilla, S. Lee, D. Carlton, and T. J. K. Liu, “Enhanced Endurance of Dual-bit SONOS NVM Cells using the GIDL Read Method, “ VLSE Tech. Symp., pp 142 ,2008.
[2.7] J. W. Han, S. W. Ryu, S. J. Choi, and Y. K. Choi, ” Gate-Induced Drain-Leakage (GIDL) Programming Method for Soft-Programming-Free Operation in Unified RAM (URAM),” IEEE Electron Device Lett., VOL. 30, NO. 2, Feb. 2009
[2.8] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[2.9] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[2.10] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge 1-x x”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[2.11] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[2.12] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS”, IEEE circuits & devices, 16, 22 (2000).
[2.13] J. S. Witters, G. Groeseneken and H. E. Maes, “Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits,” IEEE Jounal of Solid State Circuits, pp. 1372 (1989).

Chapter 3
[3.1] T. C. Lu, H. W. Zan, M. D. Ker, " Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2583-2589, Oct. 2008.
[3.2] Z. Meng, H. Chen, C. Qiu, H. S. Kwok, and M. Wong, “Active-matrix organic light-emitting diode display implemented using metal-induced unilaterally crystallized polycrystalline silicon thin-film transistors,” in SID Tech. Dig., 2001, pp. 380–383.
[3.3] K. Yoneda, R. Yokoyama, and T. Yamada, “Development trends of LTPS TFT LCDs for mobile applications,” in Proc. Symp. VLSI Circuits, pp. 85–90 (2001).
[3.4] H. Tokioka, M. Agari, M. Inoue, T. Yamamoto, H. Murai, and H. Nagata, “Low power consumption TFT-LCD with dynamic memory embedded in pixels,” in Proc. SID, pp. 280–283 (2001).
[3.5] S. I. Hsieh, H. T. Chen, Y. C. Chen, C. L. Chen, and Y. C. King, " MONOS Memory in Sequential Laterally Solidified Low-Temperature Poly-Si TFTs," IEEE Electron Device Lett., vol. 27, no. 4, pp. 272–274, Apr. 2006.
[3.6] M. Cao, T. Zhao, K. C. Sarawat, and J. D. Plummer, “A simple EEPROM cell using twin polysilicon thin-film transistors,” IEEE Trans. Electron Device Lett., vol. 15, pp. 304, (1994).
[3.7] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, C. C. Ko, S. Yang, L. W. Feng, S. M. Sze, C. Y. Chang, and C. H. Lien, “Pi-shape gate polycrystalline silicon thin-film transistor for nonvolatile memory applications,” Appl. Phys. Lett. 91, 213101, Nov. 2007.
[3.8] Y. C. Wu, M. F. Hung, C. W. Chang, and P. W. Su, “Two-bit effect of trigate nanowires polycrystalline silicon thin-film-transistor nonvolatile memory with oxide/nitride/oxide gate dielectrics,” Appl. Phys. Lett. 92, 163506, Apr. 2008.

Chapter 4
[4.1] T. C. Lu, H. W. Zan, M. D. Ker, " Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit with Temperature Compensation in LTPS Process," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2583-2589, Oct. 2008.
[4.2] K. Yoneda, R. Yokoyama, and T. Yamada, “Development trends of LTPS TFT LCDs for mobile applications,” in Proc. Symp. VLSI Circuits, pp. 85–90 (2001).
[4.3]. H. Tokioka, M. Agari, M. Inoue, T. Yamamoto, H. Murai, and H. Nagata, “Low power consumption TFT-LCD with dynamic memory embedded in pixels,” in Proc. SID, pp. 280–283 (2001).
[4.4] Y. Nakajima, “Ultra-low-power LTPS TFT-LCD technology using a multi-bit pixel memory circuit,” in Proc. SID Tech. Dig., 2006, pp. 1185–1188.
[4.5] S. I. Hsieh, H. T. Chen, Y. C. Chen, C. L. Chen, and Y. C. King, " MONOS Memory in Sequential Laterally Solidified Low-Temperature Poly-Si TFTs," IEEE Electron Device Lett., vol. 27, no. 4, pp. 272–274, Apr. 2006.
[4.6] M. Cao, T. Zhao, K. C. Sarawat, and J. D. Plummer, “A simple EEPROM cell using twin polysilicon thin-film transistors,” IEEE Trans. Electron Device Lett., vol. 15, pp. 304, (1994).
[4.7] F. Y. Jian, T. C. Chang ,A. K. Chu, T. C. Chen, S. C. Chen, C. S. Lin, H. W. Li, M. H. Lee, J. S. Chen, C. C. Shih,“Unusual threshold voltage shift caused by self-heating-induced charge trapping effect,” Electrochem. Solid-State Lett., Volume 13, Issue 4, pp. H95-H97 (2010)
[4.8] D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed. Hoboken, NJ: Wiley, 2006.
[4.9] S. Inoue, S. Takenaka, and T. Shimoda, “Study on degradation phenomenon due to a combination of contamination and self-heating in poly SI thin film transistors fabricated by a low-temperature prcess,” Jpn. J. Appl. Phys., vol. 42, pp. 4213–4217, 2003.
[4.10] H. Wang, M. Wang, Z. Yang, H. Hao, M. Wong, “Stress power dependent self-heating degradation of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors,” IEEE Transactions on Electron Devices, 2007, Vol. 54, pp. 3276-3284
[4.11] A. Valletta, A. Moroni, L. Mariucci, A. Bonfiglietti, and G. Fortunato, “Self-heating effects in polycrystalline silicon thin film transistors,” Appl. Phys. Lett. 89, 093509, Sep. 2006
[4.12] L. Wang, T. A. Fjeldly, B. Iniguez, H. C. Slade, and M. Shur, “Self-heating and kink effects in a-Si:H thin film transistors”, IEEE Trans. Electron Devices 47, 387 (2000).
[4.13] K. Takechi , M. Nakata , H. Kanoh , S. Otsuki and S. Kaneko “Dependence of self-heating effects on operation conditions and device structures for polycrystalline silicon TFTs,” IEEE Trans. Electron Devices, vol. 53, pp. 251, Feb. (2006).

Chapter 5
[5.1] T. C. Lu, H. W. Zan, M. D. Ker, " Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2583-2589, Oct. 2008.
[5.2] K. Yoneda, R. Yokoyama, and T. Yamada, “Development trends of LTPS TFT LCDs for mobile applications,” in Proc. Symp. VLSI Circuits, pp. 85–90, 2001.
[5.3] H. Tokioka, M. Agari, M. Inoue, T. Yamamoto, H. Murai, and H. Nagata, “Low power consumption TFT-LCD with dynamic memory embedded in pixels,” in Proc. SID, pp. 280–283, 2001.
[5.4] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. H. Yeh, C. F. Weng, S. M. Sze, C. Y. Chang, C. H. Lien, “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels,” Appl. Phys. Lett., vol. 90, pp.122111, Mar. 2007.
[5.5] A. J. Walker, S. Nallamothu, E.-H. Chen, M. Mahajani, S. B. Herner, M. Clark, J. M. Cleeves, S. V. Dunton, V. L. Eckert, J. Gu, S. Hu, J. Knall,M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, “3D TFT-SONOS memory cell for ultra-high density file storage applications,” in VLSI Symp. Tech. Dig., pp. 29–30, Jun. 2003.
[5.6] H. T. Lue, E. K. Lai, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu and C. Y. Lu, “A novel junction-free BE-SONOS NAND Flash,” in Proc. VLSI Symp. Tech. Dig., 2008, p. 140-141.
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Chapter 6
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