本論文提出了一個高調頻範圍，低相位雜訊與快速鎖定全積體化除整數之頻率合成器。此頻率合成器採用TSMC 0.18μm 1P6M CMOS製程並操作在1.8V供應電壓之下，主要應用於IEEE 802.11ac Wi-Fi，提供4.58GHz至5.68GHz的本地振盪器，並應用於射頻收發機的前端電路。本論文所提出的頻率合成器包含快速頻率偵測器及電荷幫浦(Fast-PFDCP)、雙模式低通迴路濾波器(Dual_Mode_LPF)、壓控振盪器(VCO)、自動選頻器(ABS)、最佳頻道選頻器(OBS)、鎖定偵測器(Lock Detector)以及含雙模數前置除頻器(dual-modulus prescaler)之pulse-swallow divider。在既有架構中使用自動選頻器來加快子頻道的選取並使用最佳頻道選頻器來產生一個具最小KVCO變化量之頻帶，此外，在壓控震盪器的設計上，利用switched capacitors技術降低VCO gain(KVCO)並能涵蓋原有所需頻帶，使得此頻率合成器能在製程、電壓、以及溫度的變化之下而能正常運作。但其缺點為需要進行兩次的鎖定動作，才能完成整個系統的運作，使得整個鎖相迴路的鎖定時間過於冗長。故本論文提出一個快速頻率偵測器及電荷幫浦(Fast-PFDCP)，藉由改良後的連續時間頻率偵測器(Continuous-Time PFD)來控制3bits電流幫浦，以提升整個鎖相迴路的鎖定速度，再加入雙模式的迴路濾波器(Dual_Mode_LPF)來穩定鎖定過程中的迴路頻寬。藉由改良後的技術可以提升45%的鎖定速度。

This thesis presents a wide tuning, low phase noise, and fast locking CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is fabricated using the TSMC 0.18μm CMOS 1P6M technology. It can be used for IEEE 802.11ac unlicensed band of Wi-Fi (Wireless Fidelity). It provides one ration frequency ranged from 4.58GHz to 5.68GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a fast-phase-frequency detector charge pump (Fast-PFDCP), a dual mode low-pass loop filter (Dual_Mode_LPF), a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), a Lock Detector, and a pulse-swallow divider. In the original design, used the ABS to reduce the calibration time by adopting the binary search algorithm to select the calibration word and used the OBS to find the optimum solution which has the minimum KVCOvariation. Furthermore, the architecture for voltage-controlled oscillator with switched capacitors technique which degrade the VCO gain (KVCO) and achieve wide tuning range and low phase noise in order to cover the desired operating frequency bands and to accommodate process, voltage, and temperature (PVT) variations. But in order to complete system operator there need twice locking action, it’s a disadvantage that PLL has large lock time. Hence, this paper presents a Fast phase frequency detector charge pump (Fast-PFDCP), control 3bits charge pump by proposed Continuous-Time PFD to enhance the locking speed of the PLL. And add Dual_Mode_LPF to stabilize the loop bandwidth in the locking process. By improved technology can enhance the locking speed of forty-five percent.

CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 4
CHAPTER 2 THE CONCEPTS OF PLLFREQUENCY SYNTHESIZER 6
2.1 General Concepts 6
2.2 Phase Frequency Detector (PFD) 7
2.2.1 Conventional Phase Frequency Detector (CPFD) 7
2.2.2 PLL with Conventional PFD 9
2.2.3 Nonlinear PFD 10
2.2.4 Piecewise-Linear PFD 12
2.2.5 Dual-Slope PFD 15
2.2.6 Summary 17
2.3 Continuous-Time Phase Frequency Detector 18
2.3.1 General Concepts 18
2.3.2 PLLs with Continuous-Time PFD 20
2.3.3 Design Considerations of Continuous-Time PFD 22
CHAPTER 3 The Proposed Frequency Synthesizer 23
3.1 Introduction 23
3.2 Fast Phase Frequency Detector Charge Pump (Fast PFDCP) 24
3.2.1 Proposed Continuous-PFD 26
3.2.2 CP_Bit_Counter 28
3.2.3 Charge Pump (CP) 29
3.3 Dual Mode Loop Filter (Dual Mode LPF) 30
3.4 Voltage Controlled Oscillator (VCO) 32
3.5 Frequency Divider 36
3.6 Auto Band Selection (ABS) 39
3.7 Optimum Band Selection (OBS) 45
3.7.1 OBS_CLK 48
3.8 Lock Detector 49
CHAPTER 4 SIMULATION RESULTS 51
4.1 RF Model and CMOS Process 51
4.2 Simulation results of PFD 52
4.3 Simulation results of VCO 54
4.4 Simulation results of Frequency Synthesizer 57
CHAPTER 5 LAYOUT AND MEASUREMENT 60
5.1 Layout 60
5.2 Measurement 61
CHAPTER 6 CONCLUSION AND FUTURE WORK 66
6.1 Conclusion 66
6.2 Future Work 66
Reference 67

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