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博碩士論文 etd-0516100-103030 詳細資訊
Title page for etd-0516100-103030
論文名稱
Title
應用於訊號處理之高速基本算術元件硬體實作
Hardware Realization of Fast Arithmetic Elements for Signal Processing Applications
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
137
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2000-05-15
繳交日期
Date of Submission
2000-05-16
關鍵字
Keywords
內積處理器、整數除法器、加法器
Carry lookahead adder, integer divider, inner product processor
統計
Statistics
本論文已被瀏覽 5780 次,被下載 1902
The thesis/dissertation has been browsed 5780 times, has been downloaded 1902 times.
中文摘要
摘 要
隨著各項訊號處理技術的蓬勃發展,高速算術運算技術的需求也因應而生。過去多年來,一般學者專家較注重於如何讓頻繁使用的算術指令加快運算如加法及乘法等,而較不重視如何改進比較罕用的指令如除法運算等。
基於加法運算為大部分的數位電路的最重要基本算術元件,我們在這篇論文中首先推出兩種以改良過的動態CMOS邏輯設計之六十四位元前看進位加法器。接著,我們提出三種新的內積運算器架構,因為在數位類神經計算中內積計算所佔的地位相當重要。同時,我們亦設計出用來建構這三種新架構之基本組成元件並解決過去設計者忽視或無法克服的問題。最後,由於整數除法仍為一些重要數位訊號處理應用中無可取代的運算,我們將提出幾個六十四位元整數除法器的架構。


Abstract
Abstract
The tremendous progress in all aspects of signal processing technology has naturally been accompanied by a corresponding development of arithmetic techniques to provide high-speed operations at reasonable complexity. In the past, many architectural design efforts have focused on maximizing performance for frequently executed simple arithmetic operations such as addition and multiplication while left other rarely used operations ignored.
In this dissertation, we firstly propose two design approaches for 64-b carry-lookahead adders (CLA) using a two-phase clocking dynamic CMOS logic since fast adders are the key elements in many digital circuits. Secondly, we place emphasis on the inner product operation since it is one of the most frequently used mathematical operations in the computation of digital neural networks. A ratioed 3-2 compressor is also presented to resolve several physical design problems that are not fully considered or implemented in previous research works. Finally we propose several fast 64b/32b integer dividers because the integer division is unavoidable in many important signal-processing applications.


目次 Table of Contents
Table of Contents
Chinese Abstract i
Abstract ii
Acknowledgments iii
List of Tables ix
List of Figures xii
1 Introduction 1
1.1 Motivation 1
1.2 Organization of the Dissertation 2
2 High-Speed All-N-Transistor Logic CMOS Adders 4
2.1 Introduction 4
2.2 All-N-Transistor (ANT) Function Unit 4
2.2.1 Sizing Problem 7
2.3 64-bit CLA 8
2.3.1 PLA-Styled CLA 8
2.3.1.1 PLA-styled 8-bit CLA 8
2.3.1.2 Speed and area analysis 9
2.3.1.3 Design of n-bit CLA adders 10
2.3.2 A Tree-Structured CLA 13
2.3.2.1 Carry-lookahead generator cell ("o" cell) 13
2.3.2.2 Speed and area analysis 15
2.3.3 Performance simulations and comparison 17
2.4 Summary 18
3 Three Alternative Architectures of Digital Ratioed Compressor 20
3.1 Introduction 20
3.2 Framework of Ratioed Compressors 22
3.2.1 Basic Compressor Building Block 22
3.2.2 Ratioed 3-2 Compressor 23
3.2.3 The First Architecture of Ratioed Compressors 26
3.2.3.1 Carry propagation delay equations 26
3.2.3.2 The count of 3-2 compressor building blocks 29
3.2.4 The Second Architecture of Ratioed Compressors 29
3.2.5 The Third Architecture of Ratioed Compressors 31
3.3 Simulation Analysis and Chip Implementation 34
3.3.1 Re-designed Building Blocks 34
3.3.2 Delay Simulations 34
3.3.3 63-6 Compressor Chip Implementation 38
3.4 Summary 42
4 High-Speed Inner Product Processors for Associative Memory
Networks 43
4.1 Introduction 43
4.2 Associative Memory Networks 44
4.2.1 Heteroassociative Network 44
4.2.2 Autoassociative Network 44
4.2.3 Bidirectional Associative Memories 45
4.3 Theory of MV-eBAM 46
4.4 Inner Product Processor for the MV-eBAM 47
4.4.1 Inner Product Term Generator 48
4.4.2 Compressor Unit 50
4.4.2.1 Framework of digital compressor design 50
4.4.3 Simulation and Analysis 51
4.4.3.1 Verilog simulations 51
4.4.3.2 Chip implementation 53
4.5 High-Speed Bipolar Binary Vector Inner Product Processor 54
4.5.1 Inner Product Term Generator 54
4.5.2 (2n-1)-to-n Compressor Unit 57
4.5.3 Bipolar-to-binary Converter 57
4.5.4 Inner Product Adjustment Unit 58
4.5.5 Performance Analysis 59
4.5.5.1 Performance analysis 59
4.5.5.2 Chip implementation 60
4.6 Summary 61
5 A Preliminary Architecture of 64b/32b Integer Divider 64
5.1 Introduction 64
5.2 Cell-based Design of 64b/32b Signed Integer Divider 65
5.2.1 Digit-Recurrence Theory 65
5.2.2 Fast Normalizer 68
5.2.2.1 Design of the fast normalizer 68
5.2.3 Radix-4 Division with a Radix-2 Selection Function 71
5.2.4 Radix-4 (High Radix) Quotient Selection Function Table 73
5.2.5 Hardware Consideration of Signed Division 75
5.2.6 Data Flow Control Unit 76
5.3 Performance Evaluation & Chip Implementation 78
5.3.1 Performance Evaluation of a 128b/64b Signed Integer Divider 78
5.3.2 64b/32b Signed/Unsigned Integer Chip Implementation 79
5.3.2.1 Pin-out assignment consideration 81
5.3.2.2 Testability design consideration 83
5.3.3 Testing the Real Chip of Integer Divider 83
5.4 Summary 84
6 Design of High-Speed 64b/32b Integer Dividers 85
6.1 Introduction 85
6.2 Mixed Radix-8/4/2 64b/32b Integer Divider 85
6.3 Mixed Radix-16/8/4/2 64b/32b Integer Divider 89
6.3.1 Operand Prescaling 90
6.3.1.1 Scaling factor calculation 91
6.3.1.2 Scaling with a 4-input CSA tree 94
6.3.2 Table Partitioning Algorithm 95
6.3.2.1 Quotient digit decomposition 95
6.3.2.2 Quotient digit assimilation unit 103
6.3.3 Dividend Prescaling 106
6.4 Radix-4/2 64b/32b Integer Divider with Quotient Digit Prediction 109
6.4.1 Estimate of the Shifted Residual 109
6.4.2 The Range of Scaled Divisor 109
6.4.3 Quotient Digit Decomposition 110
6.4.4 Quotient Digit Assimilation Unit 113
6.5 Application of Quotient Digit Prediction without Prescaling 115
6.5.1 Partitioned Quotient Digit Selection Table 115

6.5.2 Comparison with the Scheme of Quotient-digit Prediction
with Divisor Scaling 119
6.6 Summary 120
7 Conclusion 122
7.1 Summary 122
7.2 Future Work 123
References 126
Publications 135


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