嵌入式系統的發達，使得即時系統變得格外重要。其中，硬即時系統保證了整個系統的即時性，每一個任務都必須在特定時間內完成；而如何保障每個步驟都在特定時間內完成，最差執行時間是最關鍵的因素。若能算出精確的最差執行時間，那必然能保證系統的即時性。
要獲得可靠的最差執行時間，有兩個方法可以完成；第一個方法是最基本的測量分析，再來是比較可靠的靜態分析。然而，測量分析的缺點太多，可靠程度也偏低，故本論文決定以靜態分析來完成最差執行時間的測量，確保最差執行時間的可靠性。
延續[1]的研究，本論文採用SWEdish execution time tool簡稱SWEET，來做ARM處理器的最差執行時間分析。SWEET有三種不同的計算方法，針對不同的情況可以考慮使用不同的計算方法，而各種方法有各自的優點，且個種方法都有使用自己的資料結構。但由於原本的SWEET在ARM處理器針對記憶體模組建構並不完整，[1]建構了新的記憶體模組，欲提升此工具針對ARM 處理器的精確度。但是[1]的記憶體模組只能在第一個計算方法使用，剩下來的計算方法仍舊使用舊式時間模組，只考慮到指令原有的時間，並沒有對任何延遲的議題作處理。
本論文使第二個計算方法可使用[1]的記憶體模組，亦可使第二計算方法可以針對記憶體寫入寫出做分析，提升此工具在ARM處理器的精確度。

Real-time systems impose deadlines on tasks. Hard real-time systems require a guarantee that no deadline is ever missed. Such a guarantee is impossible if a program’s execution time ever exceeds its deadline. The challenge is therefore to determine the program’s worst case execution time (WCET), so the deadline can be set accordingly.
Although it is impossible to know the true WCET of most nontrivial programs, an upper bound is sufficient to guarantee that the deadline is met. Such an upper bound can be derived through a static analysis that analyzes the worst-case execution time of each portion of the source code and the worst-case flow between these portions.
One such static analyzer is the SWEdish execution time tool (SWEET). This thesis extends the work of previous students in our laboratory, who have adapted SWEET to work with the ARM processor, by fixing SWEET’s machine model [2] and memory model [1]. Despite those previous efforts, it was not possible to release the code for public use, because [1] only adapted the memory model to one of SWEET’s calculation methods (path-based). Another, more-commonly used method (IPET) was not supported. This thesis has therefore solved the problems of supporting IPET for the ARM, with the sophisticated memory model of [1].

1.Introduction 1
1.1.Deadline in Real-Time Systems 2
1.1.1. Soft Real-Time Systems 3
1.1.2. Hard Real-Time Systems 4
1.1.3. The Demand of Timing Analysis 5
1.2. Static Worst Case Execution Time Analysis 5
1.2.1. Measurement-Based Analysis 6
1.3. How [1] And [2] Added ARM Support to SWEET 7
1.4. Introducing What Is [1]’s Memory Model Done and Undone 7
1.5. How to Solve the Thing that [1]’s Memory Model Left Undone 8
2. Related Works 9
2.1.Static Analysis 9
2.1.1. Flow Facts 10
2.1.2. Flow Analysis 11
2.1.3. The Machine Model ARM9TDMI 14
2.1.4. Calculation Phase 14
2.2.Integer Linear Programming 19
2.3.SWEET 20
2.3.1. Low-Level Analysis 20
2.4.SWEET With Memory Model in Path-Based Calculation Method 23
2.5. Memory Modeling for Static Analysis 26
3. Methodology 28
3.1.The SWEET’s ILP Specification System 28
3.2.Adjusts the Architecture of SWEET 31
3.3.Understand the Structural Difference between Path-Based and Extended IPET 33
3.4. Nodes and Edges Conversion 34
3.4.1. Nodes to Nodes Conversion 35
4. Results 38
5. Conclusion 47
References 48

[1] T.-A. Chen, “A Tool for Static WCET Analysis with Accurate Memory Modeling for ARM Programs that Use Scratchpad Memory,” Master thesis, Department of Computer Science and Engineering, National Sun Yat-sen University, 2014.
[2] W.-C. Hao, “Integrating the SWEET WCET Analyzer into ARM-GCC with Extra WCFP Information to Enable WCET-Targeted Compiler Optimizations,” Master thesis, Department of Computer Science and Engineering, National Sun Yat-sen University, Taiwan, 2011.
[3] C. Burguière and C. Rochange “History-based Schemes and Implicit Path Enumeration,” 6th International Workshop on Worst-Case Execution Time Analysis, 2006.
[4] P. Raymond, “A General Approach for Expressing Infeasibility in Implicit Path Enumeration Technique,” EMSOFT IEEE, Jaypee Greens, India, 2014.
[5] R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenstrőm, “The Worst-Case Execution Time Problem – Overview of Methods and Survey of Tools,” ACM Transactions on Embedded Computing Systems, 2008.
[6] A. Ermedahl, “A Modular Tool Architecture for Worst-Case Execution Time Analysis,” VDM Verlag Publishing, Saarbrücken, Germany, 2008.
[7] SWEET (SWEdish Execution Time Tool) manual: http://www.mrtc.mdh.se/projects/wcet/sweet/DocBook/out/webhelp/index_frames.html
[8] SWEET (SWEdish Execution Time tool): http://www.mrtc.mdh.se/projects/wcet/sweet/DocBook/out/webhelp/index_frames.html
[9] J. Engblom, A. Ermedahl, M. Sjödin, J. Gustafsson, and H. Hansson, "Worst-Case Execution-Time Analysis for Embedded Real-Time Systems," International Journal on Software Tools for Technology Transfer, 2003.
[10] R. Kirner and P. Puschner, "Classification of WCET Analysis Techniques," Objective-Oriented Real-Time Distributed Computing, 2005.
[11] G. Bernat, A. Colin, and S. M. Petters, "WCET Analysis of Probabilistic Hard Real-Time Systems,” Real-Time Systems Symposium, 2002.
[12] A. Ermedahl, F. Stappert, and J. Engblom, "Clustered Calculation of Worst-Case Execution Times," International conference on Compilers, architecture and synthesis for embedded systems, 2003.
[13] WCET Benchmarks
[14] B. K. Huynh, L. Ju, and A. Roychoudhury, “Scope-aware Data Cache Analysis for WCET Estimation,” RTAS 7th IEEE, 2011.
[15] Z.Kazemi and A. M. k. Cheng, “A Scratchpad Memory-Based Execution Platform for Functional Reactive Systems and its Static Timing Analysis,” Embedded and Real-Time Computing Systems and Applications, IEEE 22nd International Conference, 2016.
[16] C. Ferdinand, C. Cullmann, G. Gebhard, D. Grund, C. Maiza, J. Reineke, B. Triquet, and R. Wilhelm, ” Predictability Considerations in the Design of Multi-Core Embedded Systems,” Proceedings of Embedded Real Time Software and Systems, 2010.
[17] A. Prakash and H. D. Patel, “An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013.
[18] C. A. Healy, D. B. Whalley, and M. G. Harmon, “Integrating the Timing Analysis of Pipelining and Instruction Caching,” Real-Time Systems Symposium 16th IEEE, 1995.
[19] F. Mueller and D. B. Whalley, “Fast Instruction Cache Analysis via Static Cache Simulation,” Simulation Symposium, 1995.
[20] J.-Y., Bai, “A Memory-Realistic SPM Allocator with WCET/ACET Tunable Performance,” Master thesis, Department of Computer Science and Engineering, National Sun Yat-sen University, 2010.
[21] T. Lundqvist, “A WCET Analysis Method for Pipelined Microprocessors with Cache Memories,” Chalmers University of Technology, 2002.
[22] R. Bourgade, C. Ballabriga, H. Casse, C. Rochange, and P. Sainrat, “Accurate Analysis of Memory Latencies for WCET Estimation,” 16th International Conference on Real-Time and Network Systems, 2008.