本研究主要對於a-IGZO薄膜電晶體的熱載子效應與自熱效應在對稱電極與非對稱電極結構下之劣化機制探討，首先討論對稱電極結構之熱載子效應造成之劣化行為，發現在熱載子電應力施加(hot carrier stress, HCS)過後其飽和區的ID-VG曲線出現了因閘極施加正偏壓誘發電子捕獲在閘極絕緣層或IGZO/閘極絕緣層介面導致的正向的VT-shift，且reverse mode有on-state 電流與S.S.劣化，這是因為有缺陷能階產生在靠近汲極端造成的。且非對稱電極結構U型汲極/I型源極模式的熱載子效應劣化機制與對稱電極結構是由相同的劣化機制主導其劣化行為，但在非對稱電極結構薄膜電晶體之I型汲極/U型源極模式的HCS看到不同劣化行為，其飽和區的ID-VG曲線顯示出reverse mode有因尖端效應造成汲極端有強電場誘發大量電子捕獲而出現的嚴重的正向VT-shift，且在CGD、CGS單邊電容量測可以看見因汲極端有大量電子捕獲產生的兩階段電容抬升行為。並使用ISE-TCAD電性模擬軟體模擬得到相同的結果。
而在升溫的熱載子效應，於低溫時所產生的on-state 電流與S.S.劣化會隨著溫度的上升而消失，並會出現CGD單邊電容量測出現了電容提前導通的情形，且不論是對稱電極結構或非對稱電極結構之薄膜電晶體都會發生此種 on-state 電流與S.S.劣化消失的行為。
最後我們探討自熱效應在對稱電極與非對稱電極結構上之劣化機制，對稱電極結構薄膜電晶體的自熱效應產生之劣化行為主要是由汲極端通道電阻較大造成溫度較高而有較源極端多的電子捕獲使飽和區ID-VG曲線的reverse mode有較大的VT-shift以及缺陷能階產生在源極端導致的on-state 電流劣化。至於非對稱電極結構I型汲極/U型源極模式薄膜電晶體的自熱效應劣化機制與對稱締結構是相同的。而非對稱電極結構U型汲極/I型源極模式薄膜電晶體的自熱效應劣化則是由較多的電子捕獲在源極端所主導，且非對稱電極結構的劣化會較對稱電極結構來得嚴重。

In the first section, we investigate the hot-carrier effect in indium–gallium–zinc oxide (IGZO) thin film transistors with symmetric and asymmetric source/drain structures. The different degradation behaviors after hot-carrier stress in symmetric and asymmetric source/drain devices indicate that different mechanisms dominate the degradation. The degradation behaviors under hot-carrier stress in InGaZnO thin film transistors with symmetric electrodes indicate on-state current and subthreshold swing degradation, which are only observed in ID-VG transfer curve under reverse mode. This is believed that impact ionization is taken place near the drain side and induced trap states generation. The same stress condition with a U-shaped drain and I-shaped source, the degradation behaviors of I-V and C-V curves are quite similar to the results of the symmetric structure. It is worthy to note the degradation behaviors after the hot-carrier stress with I-shaped drain and U-shaped source. The ID-VG curve under forward-operation mode exhibit a parallel shift caused by electron trapping. Furthermore, the parallel shift is more pronounced under reverse-operation mode, which can be ascribed to more evident electron-trapping at the IGZO/gate dielectric interface or within the gate dielectric layer. The location of trapped electron is estimated from the two-stage rise in the gate-to-drain/gate-to-source capacitance curves and then verified by the simulation tool.
In the second section, we extend the previous chapter about hot-carrier stress in a-InGaZnO TFT. The hot-carrier stress performed at elevated temperatures are performed with VG = 10 V and VD = 25 V. With the increasing of stress temperature, on-state current degradation in the I-V transfer curve under reverse mode is gradually suppressed, and the abnormal hump in the gate-to-drain capacitance-voltage curvebecomes more severe. These suppressed degradations and the more severe hump can be both attributed to hole-trapping near the drain side due to high drain bias at high temperature.
To investigate the self-heating effect in a-InGaZnO TFT, the stress condition is performed with VG = 25 V, VD = 15 V and a grounded source. After self-heating stress, it is found that the threshold voltage shift is more severe than positive gate bias with VG = 25 V. This additional VT-shift can be attributed to Joule-heating generated by self-heating operation. However, the different degradation behaviors are found after I-shaped drain/U shaped source and U-shaped drain/I-shaped source operation. These phenomena are attributed to non-uniform Joule-heating distribution in the channel under self-heating operation. However, the I-shaped drain/U-shaped source induced more serious VT shift than symmetric structure and U-shaped drain/I-shaped source. These results exhibit that I-shaped drain induce higher channel temperature than others operation.
Keyword: Thin Film Transistors, Hot Carrier Effect, InGaZnO, Self-Heating Effect, kick back voltage, Threshold voltage, charge trapping.

誌謝 ii
摘要 iv
Abstract vi
目錄 viii
圖次 ix
第一章.序論 1
1.1研究背景 1
1.2主動層材料性質與優劣比較 2
1.3為何選擇a-IGZO? 4
1.4研究動機 5
第二章.元件結構與基本電性 12
2.1元件結構 12
2.2元件基本特性 13
2.2.1電晶體輸出特性與轉換特性曲線 13
2.2.2電容-電壓轉換特性 13
第三章.參數萃取與儀器介紹 19
3.1參數萃取 19
3.1.1電流與載子遷移率 19
3.1.2臨界電壓(VT) 20
3.1.3次臨界擺幅(Subthreshold swing, S.S.) 21
3.2 儀器介紹 22
第四章.對稱與非對稱電極結構之熱載子效應 25
4.1簡介 25
4.2實驗架構 26
4.3 結果與討論 27
4.3.1室溫下的對稱與非對稱結構之熱載子效應 27
4.3.2升溫的對稱與非對稱電極結構之熱載子效應 30
4.3.3非對稱I/U電極結構之升溫熱載子效應 36
4.4.總結 39
第五章.對稱與非對稱電極結構之自熱效應 70
5.1簡介 70
5.2實驗架構 71
5.3實驗結果與討論 72
5.3.1對稱電極結構薄膜電晶體之自熱效應 72
5.3.2非對稱I/U電極結構薄膜電晶體之自熱效應與尺寸效應 74
5.4總結 80
第六章.結論 99
Reference 101

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