本論文採用TSMC 90nm製程技術，提供一個在操作電壓0.5V下，取樣頻率每秒50萬次、10位元應用於生物訊號的逐漸逼近式類比數位轉換器。此電路可以應用於物聯網相關的感測器或監控裝置上，達到小面積、低功秏與低成本的目標。
在逐漸逼近式類比數位轉換器設計中，為了能讓拆分合併架構提供的效能更上一層樓，因此使用了降低電容陣列功率消耗的設計。另外也使用了動態鎖存型比較器的架構，以減少靜態功率消耗。另外，在電容設計方面，採用了榫眼結構的 MOM 電容，利用減少單位電容的寄生電容效應、分佈式的連接單位電容，這樣可以減少電容陣列中的開關能量消耗，更可以改善電容陣列面積過大的問題。
本論文最終提出一個輸入訊號為 500 Ks/s，SNDR 為 56.11 dB，有效位數為 9.028 位元，微分非線性誤差 (DNL) 為 0.412/-0.435 LSB，積分非線性誤差 (INL) 為 0.590/-0.767 LSB，所消耗的功率為 1.5003μW。

This thesis presents a 10-bit 500 KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for biomedical application with a 0.5 V supply voltage which is implemented by using the TSMC 90nm process technology. The circuit can be applied to the sensors or monitoring device related to the Internet-of-Things (IoT). This design can achieve the purpose of low area, low power and low cost.
In order to provide a better performance and the reduced DAC switching energy, the merge and split (MS) switching architecture is implemented. The dynamic latching comparators are used to reduce the static power consumption. A MOM capacitor with a Mortise-Tenon structure is used to reduce the parasitic capacitance effect in a single capacitor and the distributed connected unit capacitors. They can reduce the switching energy consumption in the capacitor array and improve the overlarge area of the capacitor array problem.
The simulated results show that the sampling rate can be 500Ks/s, the SNDR is 56.11 dB, and ENOB is 9.028 bit. The DNL and INL are 0.412/-0.435 LSB and 0.590/-0.767 LSB, respectively. The power consumption is 1.5003μW.

論文審定書..................................................................................................................... i
中文摘要........................................................................................................................ ii
Abstract ........................................................................................................................ iii
目錄 ............................................................................................................................. iv
圖目錄........................................................................................................................ viii
表目錄.......................................................................................................................... xii
Chapter 1. 緒論 ............................................................................................................. 1
1.1 背景.................................................................................................................... 1
1.2 研究動機與目標................................................................................................ 3
1.3 論文組織架構.................................................................................................... 4
Chapter 2. 基本架構與原理 ......................................................................................... 5
2.1 類比數位轉換器基本原理................................................................................ 5
2.2 常見的類比數位轉換器架構............................................................................ 6
2.2.1. 快閃式類比數位轉換器 (Flash ADC) ............................................. 6
2.2.2. 兩階段式類比數位轉換器 (Two Step ADC) .................................. 7
2.2.3. 二元搜尋式類比數位轉換器 (Binary Search ADC) ....................... 8
2.2.4. 管線式類比數位轉換器 (Pipeline ADC) ........................................ 9
2.3 連續漸進式類比數位轉換器 (Successive Approximation ADC) ................ 11
2.3.1. 傳統式連續漸進式類比數位轉換器 (Conventional SAR ADC) . 13
2.3.2. 單調式連續漸進式類比數位轉換器 (Monotonic SAR ADC). .... 15
2.3.3. 平均充電式連續漸進式類比數位轉換器 (Charge-Average Switching SAR ADC).................................................................................. 17
2.3.4. 拆分合併式類比數位轉換器 (Merge and Split SAR ADC) ......... 18
2.3.5. 連續漸進式類比數位轉換器之架構比較...................................... 19
2.4 類比數位轉換器的特性參數.......................................................................... 21
2.4.1. 動態效能 (Dynamic Performance) ................................................. 21
2.4.2. 靜態效能 (Static Performance) ...................................................... 23
2.4.3. 其他相關參數.................................................................................. 25
Chapter 3. 目標架構電路設計介紹 ........................................................................... 30
3.1 設計考量.......................................................................................................... 30
3.2 新型榫眼結構電容(Mortise-Tenon Structure) ............................................... 30
3.3 比例電容佈局生成.......................................................................................... 33
3.3.1. 電容陣列的大小計算...................................................................... 34
3.3.2. 電容放置及全局佈線...................................................................... 34
3.3.3. 詳細的佈線...................................................................................... 40
3.4 應用於拆分合併式與三級開關之電容陣列.................................................. 41
3.5 切換能量分析.................................................................................................. 43
3.5.1. 電容陣列開關能量分析.................................................................. 43
3.5.2. 應用於SAR ADC之架構開關能量分析 ...................................... 44
Chapter 4. 目標類比數位轉換器之實現 ................................................................... 49
4.1 取樣保持電路 (Sample and Hold Circuit, S/H) ............................................. 52
4.1.1. 簡易型取樣保持電路...................................................................... 53
4.1.2. 導通電阻Ron設計考量................................................................... 54
4.1.3. 傳統拔靴式開關 (Bootstrapped Switch) ....................................... 54
4.1.4. 兩階段拔靴式開關 (Two-step Bootstrapped Switch) ................... 56
4.1.5. 取樣保持電路之佈局...................................................................... 58
4.2 比較器 (Comparator) ...................................................................................... 59
4.2.1. 比較器電路設計.............................................................................. 59
4.2.2. 比較器之佈局.................................................................................. 62
4.3 時脈產生器 (Clock Generator) ...................................................................... 63
4.3.1. D型正反器 (D Flip-Flop) .............................................................. 64
4.3.2. 時脈產生器設計.............................................................................. 65
4.3.3. 時脈產生器之佈局.......................................................................... 66
4.4 邏輯控制電路 (SAR Control Logic).............................................................. 67
4.4.1. 電容陣列數位類比轉換器邏輯控制電路 (CDAC Control Logic) 67
4.4.2. 拔靴式開關 (Bootstrapped Switch) ............................................... 69
4.4.3. 拆分合併開關 (Merge and Split Switch) ....................................... 70
4.5 單位電容與電容陣列佈局設計...................................................................... 72
4.5.1. MOS電容 (Metal-Oxide-Semiconductor Capacitor) ..................... 72
4.5.2. MIM電容 (Metal-Insulator-Metal Capacitor) ............................... 73
4.5.3. MOM電容 (Metal-Oxide-Metal Capacitor) .................................. 73
4.5.4. 電容陣列 (Capacitor Array) ........................................................... 77
4.6 數位訊號同步輸出電路D-latch..................................................................... 79
4.7 類比數位轉換器之全電路佈局...................................................................... 80
Chapter 5. 效能與模擬結果 ....................................................................................... 82
5.1 快速傅立葉轉換測試 (Fast Fourier Transform, FTT) .................................. 82
5.2 模擬結果與比較分析...................................................................................... 84
5.2.1. 靜態分析.......................................................................................... 86
5.2.2. 動態分析.......................................................................................... 89
5.2.3. 規格表比較...................................................................................... 90
Chapter 6. 結論 ........................................................................................................... 92
6.1 結論.................................................................................................................. 92
6.2 未來展望.......................................................................................................... 92
6.3 待改進之處...................................................................................................... 93
參考文獻...................................................................................................................... 98

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