本論文提出之具製程與電壓變異補償之漏電流抑制兩倍電壓輸出緩衝器，係
為了避免傳輸兩倍電壓準位時導致閘極過壓問題，在輸出級使用電晶體堆疊的技
術。此外，在輸出級使用臨界電壓較低的電晶體使整體電壓迴轉率上升，於補償
路徑的電晶體使用臨界電壓較高的電晶體來抑制漏電流，同時增加輸出級MOS
的長度。因此，本論文提出漏電流與電壓迴轉率折衷之最佳設計方式。而為了降
低電壓迴轉率的變異量，另提出一新型製程偵測器，能在高速傳輸前就達到製程
偵測並進行補償，使電壓迴轉率的補償效果，經量測證實可達到20% 以上。

本論文另提出低雜訊電流平衡式儀表放大器，係有別於一般傳統式儀表放大
器使用太多的電阻，導致雜訊太大而影響精確性和穩定性。本論文提出使用電流
平衡式儀表放大器架構，並改良轉導級與轉阻級電路。此外，轉導放大器設計一
電流調節放大器，使電流更加穩定並減少不必要的電流鏡堆疊設計，達到低雜
訊、高開迴路增益、高共模拒斥比。

A leakage reduction 2×VDD output buffer with compensation to process and voltage
variation is firstly proposed in this thesis. The proposed circuit architecture consists of
two parts: process and voltage compensation circuit and output buffer. When digital signal
with two times of supply voltage levels, the output stage of the buffer utilizes stacked
MOSFETs to prevent the gate-oxide overstress. In addition, an approach of leakage current
reduction for the output stage, including MOSFETs type selection and MOSFETs
length tuning, is proposed. An optimal solution between leakage current and the slew rate
is disclosed. To avoid the slew rate deviation, a novel process detector is also proposed to
quickly detect the variation. The improvement of the slew rate deviation is reduced by at
least 20% by measurements.

A low noise current-balancing instrumentation amplifier is the second research topic
in this thesis. Traditional instrumentation amplifiers are suffered from large noise since
many resistors are used. We propose a current-balancing instrumentation amplifier where
the transconductance stage and the transimpedance stage use fewer resistors, especially the
transconductance stage with an electronics tuning amplifier such that the current mirror is
more stabilized and the height of the stacked resistors is reduced. Therefore, the currentbalancing
instrumentation amplifier attains low noise, high gain, and high CMRR.

論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
論文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1 概論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 相關文獻與研究探討. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 具PVTL 補償兩倍電壓輸出緩衝器. . . . . . . . . . . . . . . 4
1.2.2 儀表放大器. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.1 具製程與電壓變異補償之漏電流抑制兩倍電壓輸出緩衝器. . 9
1.3.2 低雜訊電流平衡式儀表放大器. . . . . . . . . . . . . . . . . . 9
1.4 論文大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 具製程與電壓變異補償之漏電流抑制兩倍電壓輸出緩衝器. . . . . . . . . 11
2.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 電路架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 輸出緩衝器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 VDDIO 偵測電路. . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.2 電壓準位轉換器. . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.3 前置驅動電路. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.4 輸出級. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 製程與電壓偵測補償電路. . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.1 NMOS 變異偵測器. . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.2 PMOS 變異偵測器. . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.3 電壓變異偵測器. . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.4 數位邏輯電路. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5 電路模擬與預計規格. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5.1 補償電路與最高傳輸速度模擬. . . . . . . . . . . . . . . . . . 27
2.5.2 預計規格. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.6 晶片實作與量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.1 晶片照相. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.2 量測環境. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.3 晶片量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.7 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3 低雜訊電流平衡式儀表放大器. . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 低雜訊電流平衡式儀表放大器電路設計. . . . . . . . . . . . . . . . . 45
3.2.1 輸入級與轉阻級. . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.2 轉導級. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2.3 輸出級. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3 電路模擬與預計規格. . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.1 電路規格模擬. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.2 雜訊模擬. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.3 溫度對儀表放大器之影響. . . . . . . . . . . . . . . . . . . . 53
3.3.4 預計規格. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4 結論與未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.1 具製程與電壓變異補償之漏電流抑制兩倍電壓輸出緩衝器. . . . . . 57
4.2 低雜訊電流平衡式儀表放大器. . . . . . . . . . . . . . . . . . . . . . 58
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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