穿隧式電晶體將會是低耗電元件的首選，其具有較高的開關電流比、極陡峭的次臨界斜率以及較低漏電流。傳統穿隧式電晶體的導通電流比傳統的反轉式電晶體來的低。許多專家模擬出許多不同結構並改善穿隧電流不夠的缺點，但鮮少人有實際的製作出元件並詳細討論可靠度分析。
在本篇碩士論文中，提出多晶矽通道厚度對穿隧式電晶體影響之研究，首先將相同製程條件下，以50nm與100nm的厚度做特性轉換曲線(ID-VG)圖中，發現較薄通道擁有較低的漏電流、較高的導通電流與較好的次臨界斜率。在輸出曲線(ID-VD)圖中，在大閘極偏壓會有負電阻的效應，是因為熱載子效應造成，使輸出電流降低。傳統電晶體在的微縮過程，會有短通道效應，進而研究穿隧式電晶體對通道長度的影響，發現長度由20μm到1μm的元件之次臨界斜率變動量非常小，導通電流與截止電流也都與通道長度維持一定關係，說明對穿隧式電晶體擁有很好的短通道抑制能力。
為了詳細區分元件劣化的過程，將分成三個部分做討論。第一是純溫度效應的影響，分成25、75 與125 (℃)，發現多晶矽薄膜內的補陷電荷將嚴重受到溫度影響，導致漏電流的上升與次臨界斜率的倒塌。第二部分則是正偏壓應力中，驅使電壓分別為3、4、5 (V)，將與傳統電晶體劣化機制完全不同，是閘極與源極重疊區的垂直電場造成表面狀態電荷，詳細將在本論文中討論。最後再做正偏壓溫度不穩定性的討論。
經過一系列的結果分析，改變通道厚度確實可以提升穿隧式電流與次臨界斜率。藉由可靠度討論後，未來可以藉由結果進行結構的改善。因此，穿隧式薄膜電晶體確實是未來綠色能源元件。

Tunneling field-effect transistors(TFET),as promising candidates for less power hungry devices, have large ON/OFF ratio, steep subthreshold slope and low leakage current. For convention TFET ,on-state current is general much lower than that of inversion-mode devices. Many experts simulated with different structure and improved the disadvantages of low tunneling current. However, very few people have already produced devices and demonstrated result of reliability analysis detailedly.
In the same production condition, the transfer characteristic of thickness of 50nm and 100nm were investigated, it is exhibited that more thinner channel film thickness had low off-leakage, more high on-state current and steep subthreshold swing. In the output It make output-current reduced, because of the hot carrier effect inducing. For Convention MOSFETs scaling down, the short channel effect will be more serious. Sequentially, TFET with length(20μm via 1μm) was examined that show better immunity of short channel effect in our experiment.
To distinguish the mechanism of device degradation, the result will be divided into three sections to discuss. At First, pure temperature effect condtion:25、75 and 125℃ were found that trap charge in poly-si thin film was seriously influenced by raising temperature. It leaded to leakage current raised and subthreshold swing degraded. And the second section, the positive bias stress, overderive voltage condition : 3、4、5(V), it was totally different mechanism to inversion-mode devices. It indicated that the vertical field at gate/source overlap region caused interface-state trap. The details will be discussed in the thesis. Finally, positive-bias temperature instability(PBTI)was explained.
Through these results and analysis, changing channel thickness could exactly improve tunneling current and subthreshold slope. After discussing by the reliability, the structure can be improved by the result in the future . Therefore ,TFET are exactly low power devices in the future .

目錄
論文審定書 i
論文公開授權書 ii
致謝 iii
摘要 iv
Abstract v
圖目錄 viii
表目錄 xii
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 3
1.3 多晶矽薄膜電晶體 4
1.4 多晶矽薄膜電晶體之漏電流機制 4
1.5 短通道效應 5
1.5.1汲極導致能障下降(Drain-Induced Barrier Lowering) 5
1.5.2擊穿崩潰(Punch-Through) 6
1.6 通道厚度效應 6
1.7 穿隧式電晶體 7
1.7.1 操作與機制 7
1.7.2 穿隧電晶體的性能提升與改善 7
1.7.3 穿隧式薄膜電晶體 8
第二章 元件製作與實驗步驟 19
2.1 元件參數萃取方式 19
2.1.1 臨界電壓(Threshold Voltage) 19
2.1.2 次臨界擺幅(Subthreshold Swing) 19
2.3 實驗方法與步驟 20
第三章 結果與討論 28
3.1 穿隧式薄膜電晶體之常溫電性分析 28
3.2 穿隧式薄膜電晶體可靠度分析 29
3.2.1 穿隧式薄膜電晶體之變溫分析 29
3.2.2 穿隧式薄膜電晶體在常溫下之正偏壓應力分析 30
3.2.3 穿隧式薄膜電晶體在正偏壓溫度不穩定性分析 31
第四章 總結與未來展望 47
參考文獻 48
簡歷(Vita) 50
Publication List 51

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