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博碩士論文 etd-0606117-164916 詳細資訊
Title page for etd-0606117-164916
論文名稱
Title
低耗能存取之5T與6T單端讀寫無負載式靜態隨機存取記憶體
A Single-ended 5T and 6T Load-less SRAM with Low Energy Access
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
77
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2017-06-21
繳交日期
Date of Submission
2017-07-06
關鍵字
Keywords
單端讀寫、無負載式、靜態隨機存取記憶體、存取能量損耗、漏電流
energy per access, load-less, single-ended, leakage current, static random access memory
統計
Statistics
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The thesis/dissertation has been browsed 5700 times, has been downloaded 46 times.
中文摘要
本論文包含兩個研究主題,分別為低耗能存取之5T 與6T 單端讀寫無負載式靜態隨機存取記憶體電路,皆使用TSMC 28 nm CMOS LOGIC High Performance Mobile Computing ELK Cu 1P10M 0.9&2.5 V(TN28HPM) 製程實現。
首先,本論文研究以超高門檻電壓P 型電晶體以及超低門檻電壓N 型電晶體,實現先前文獻提出之單端讀寫無負載式5T 無負載式靜態隨機存取記憶體,分析漏電流對於此5T 記憶體單元架構的影響,並改善先前文獻提出之補償電路。補償電路架構由自我調適電壓偵測器與半時脈週期提升字元線電壓電路組成,用以降低存取之能量損耗,並以兩個相同1 kb 的5T 記憶體陣列來展現其補償電路的效能。量測結果為操作頻率50 MHz 下,其存取耗能從223.2 fJ 降為83.2 fJ,改善62.72%,讀取延遲時間改善15.28%,功率延遲乘積從267.84 fJ 降為84.57 fJ,
改善68.42%。
另外,本論文針對單端讀寫無負載式5T 無負載式靜態隨機存取記憶體單元改良為單端讀寫無負載式6T 無負載式靜態隨機存取記憶體單元,係為了解決前述5T 記憶體電路受到漏電流破壞記憶體單元內部儲存資料。因此加入一PMOS
電晶體形成漏電流路徑,確保6T 記憶體單元內儲存資料不會受到漏電流破壞。單端讀寫無負載式6T 無負載式靜態隨機存取記憶體電路以前述相同之補償電路進行補償,佈局後模擬結果之存取耗能平均改善1.57%,讀取延遲時間平均改善3.18%,功率延遲乘積平均改善4.8%,存取耗能為66 fJ。
Abstract
This thesis covers two topics, including single-ended 5T and 6T load-less SRAMs with low energy access. Prototypes of the two designs are realized using TSMC 28 nm CMOS LOGIC High Performance Mobile Computing ELK Cu 1P10M 0.9&2.5 V Process。
A single-ended 5T load-less SRAM, where ultra-high Vth PMOS is used as data latch and ultra-low Vth NMOS is applied as access switch, is proposed firstly to suppress the impact of the leakage. A power-delay product compensation circuit is added to reduce the energy per access of the SRAM. Two identical 1 kb memory arrays are realized on the
same die to prove the performance of the compensation circuit. At a 50 MHz operating
frequency, the measurent result of energy per access, read delay, power-delay product are
reduced by 62.72%, 15.28%, 68.42%, respectively, and the energy per access is dropped to 83.2 fJ from 223.2 fJ and power-delay product is dropped to 84.57 fJ from 267.84 fJ.
Moreover, another single-ended 6T load-less SRAM is also proposed to further reduce the impact of the leakage in the single-ended 5T load-less SRAM. To ensure the data state in the SRAM cell is not destroyed, another PMOS is added to become a ground path of leakage current. The compensation circuit of the single-ended 6T load-less SRAM is the same as that of the single-ended 5T load-less SRAM. Post-layout simulation results of energy per access, average read delay, average power-delay product are improved 1.57%, 3.18%, 4.8%, respectively, and the energy per access becomes 66 fJ.
目次 Table of Contents
論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
論文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
1 研究背景與動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 相關文獻與研究探討. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 靜態隨機存取記憶體單元. . . . . . . . . . . . . . . . . . . . 4
1.2.2 記憶體單元補償電路. . . . . . . . . . . . . . . . . . . . . . . 11
1.3 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 論文大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 低耗能存取之5T 單端讀寫無負載式靜態隨機存取記憶體. . . . . . . . . . 15
2.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 低耗能存取之5T 記憶體電路系統架構. . . . . . . . . . . . . . . . . 15
2.3 低耗能存取之5T 記憶體電路設計. . . . . . . . . . . . . . . . . . . . 17
v
2.3.1 單端讀寫無負載式5T 記憶體單元電路. . . . . . . . . . . . . 17
2.3.2 列架構之共享式記憶體單元. . . . . . . . . . . . . . . . . . . 23
2.3.3 行解碼器與列解碼器. . . . . . . . . . . . . . . . . . . . . . . 24
2.3.4 功率延遲乘積補償電路. . . . . . . . . . . . . . . . . . . . . . 25
2.3.5 控制電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.6 內建自我測試電路. . . . . . . . . . . . . . . . . . . . . . . . 30
2.4 晶片佈局. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5 佈局後模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.1 記憶體單元佈局後模擬. . . . . . . . . . . . . . . . . . . . . . 33
2.5.2 記憶體電路佈局後模擬. . . . . . . . . . . . . . . . . . . . . . 35
2.5.3 預計規格與模擬結果比較. . . . . . . . . . . . . . . . . . . . 38
2.6 晶片量測結果與文獻比較. . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6.1 量測環境與設定. . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6.2 量測結果與分析. . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6.3 佈局後模擬結果與量測結果比較. . . . . . . . . . . . . . . . 43
2.7 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3 低耗能存取之6T 單端讀寫無負載式靜態隨機存取記憶體. . . . . . . . . . 46
3.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
vi
3.2 低耗能存取之6T 記憶體電路系統架構. . . . . . . . . . . . . . . . . 46
3.3 單端讀寫無負載式6T 記憶體單元. . . . . . . . . . . . . . . . . . . . 47
3.4 晶片佈局. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5 佈局後模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5.1 記憶體單元佈局後模擬. . . . . . . . . . . . . . . . . . . . . . 51
3.5.2 記憶體電路佈局後模擬. . . . . . . . . . . . . . . . . . . . . . 53
3.5.3 佈局後模擬結果與文獻比較. . . . . . . . . . . . . . . . . . . 56
3.6 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4 結論與未來工作. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.1 研究成果與結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2 未來研究規劃. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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