近年來使用聚合物-金屬及金屬-金屬間接合之方式，在封裝結構之應用領域展現日漸重要的趨勢。尤以晶圓級晶片尺寸封裝(WLCSP)製程具有高度系統整合而受到重視，但高分子介電材料在與重新佈線層(RDL)間因熱膨脹係數不匹配將易導致裂縫產生，而造成元件失效。因此，高分子介電材料的機械性質探討與構裝體的應力分佈分析能使可靠度提升是一重要的研究項目。於IC封裝過程中，有許多因素影響元件的穩定性與可靠度，如溫度、熱膨脹係數、應力、材料的楊氏係數等材料特性的影響下使得封裝結構發生翹曲變形(Warpage)、破裂(Crack)與脫層(Delamination)等問題。然而於過去研究中，對於封裝結構的翹曲變形、基板脫層等有許多探討，但針對多層封裝的脫層問題較少論及。
本論文將針對無凸塊底層(UBM)之晶圓級晶片尺寸封裝結構造成的介電層與重新佈線層所產生脫層的裂縫下，利用奈米壓痕試驗機進行介電層之高分子材料機械性質的測試、再利用有限元素分析軟體ANSYS建立一簡易WLCSP的模型，模擬封裝結構於熱負載下的熱應力與熱應變行為、最後藉由均勻實驗設計法的設計，再建立Kriging模型與反應曲面進行參數最佳化調整，求得較佳製程參數，並以此較佳製程參數帶入所建立之模型進行模擬。模擬顯示經實驗設計法調整後的參數可使其熱應力由86.3 MPa 降低至51.5MPa下降。Kriging模型預測與ANSYS模擬預測其誤差為3.7%。

Recently, adopting the polymer-metal and metal-metal combination in the application of package shows the incremental importance. Among of the packaging process, the wafer level chip scale packaging (WLCSP) process with high integration of system was taken seriously. However, the mismatched thermal expansion coefficient between polymer dielectric material and redistribution layer (RDL) can result in the generation of crack which can make element be dysfunctional. Therefore, the investigation of mechanical characteristics of polymer dielectric material and analysis of stress distribution of package can be used to improve the reliability. For the past research, the warpage and delamination of package structure were investigated widely. However, the delamination of multi-layer package was less investigated.
In this study, the delamination between the dielectric layer and RDL is resulted from the under bump metallization (UBM)-free WLCSP. The nanoindentation is adopted to test the mechanical characteristics of polymer dielectric material. Then, the WLCSP model was built by using finite element analysis, ANSYS, and is used to simulate the thermal stress and thermal strain of package structure under thermal loading. Finally, the uniform design method with Kriging model and response surface methodology was used to obtain the optimal experimental parameter which is substituted into the built model and simulated. From the result of simulation, the thermal stress decrease from 86.3 MPa to 51.5 MPa with the optimal parameter. The error between Kriging and ANSYS simulation was 3.7%.

致謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 viii
表目錄 x
第一章 緒論 1
1.1 前言 1
1.2 研究背景 2
1.2.1 IC封裝技術 2
1.2.2 晶圓級晶片尺寸封裝 4
1.3 研究動機與目的 6
1.4 文獻回顧 7
1.5 本文架構 8
第二章 理論基礎與原理 9
2.1 奈米壓痕技術 9
2.1.1 奈米壓痕基本概述 9
2.1.2 奈米壓痕理論 10
2.1.3 探針特性 12
2.1.4 連續勁度量測技術 (CSM) 14
2.2 均勻設計實驗法 17
2.2.1 實驗設計 17
2.2.2 均勻設計實驗法概論 18
2.2.3 均勻設計表 18
2.2.4 均勻設計實驗法程序 21
2.2.5 均勻設計實驗法結果分析 21
2.3 克利金模型插值法 (Kriging method) 22
2.4 Kriging 反應曲面 22
第三章 研究方法 25
3.1 實驗架構 25
3.2 實驗設備─ MTS XP 奈米壓痕試驗機 26
3.3 有限元素分析 28
3.3.1 模型架構 28
3.3.2 基本假設 30
3.3.3 邊界拘束條件與負載 30
3.3.4 ANSYS有限元素分析 32
第四章 均勻實驗法最佳化分析 34
4.1 參數設計 35
4.2 均勻設計表選擇 37
4.3 建立Kriging模型與反應曲面 38
4.4 熱應力之Kriging模型建立 39
4.5 熱應力最佳化分析方法 40
第五章 實驗結果與討論 42
5.1 壓痕機械性質分析 42
5.1.1 楊氏係數 43
5.1.2 硬度 46
5.2 數值模擬結果分析 47
5.2.1 相同介電層材料之單一溫度模擬分析 47
5.2.2 相異兩層介電層材料性質之熱應力分析 52
5.3 均勻設計實驗法之數值分析與統計 55
5.3.1 均勻設計實驗結果 55
5.3.2 均勻設計實驗線性回歸分析 56
5.4 Kriging 反應曲面 57
5.5 製程參數最佳化分析 61
5.6 最佳化參數之熱應力模擬分析 61
5.7 模型驗證 62
第六章 結論與未來方向 63
參考文獻 65

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