輸入輸出緩衝器在高速介面中為不可或缺之技術，晶片間之訊號交換必須仰賴其作為溝通橋梁。然而隨著製程的進步，各種傳輸規格對於供應電壓以及電壓迴轉率的限制越來越嚴謹。故本論文提出兩個設計，分別為具製程、電壓、溫度以及漏電流補償之混合電壓輸出緩衝器，與具電壓迴轉率補償之混合電壓輸入輸出緩衝器。

本論文提出之具製程、電壓、溫度以及漏電流補償之混合電壓輸出緩衝器，為了傳輸多種電壓準位，輸出級使用堆疊式電晶體技術，可避免高傳輸電壓引發之閘極氧化層過壓、漏電流路徑等問題。為了降低電壓迴轉率變異量，提出新型之PVT變異偵測器，分別對PMOS 以及NMOS 之PVT 角落進行偵測。此外藉由漏電流補償，可降低輸出級造成之暫態電流。本設計之電壓迴轉率補償效果，經量測證實為22%以上。

本論文另提出之具電壓迴轉率補償之混合電壓輸入輸出緩衝器，相較於第一個設計，輸入輸出緩衝器具備雙向傳輸之能力，可根據輸入訊號切換其工作模式。同時改進PVT變異偵測器，以並聯式架構取代先前設計，可降低製程偵測之誤差、提升其全角落偵測之準確度。本設計之電壓迴轉率補償效果經模擬結果顯示，可達38.3%以上。

I/O buffer is a critical component for high-speed interfaces. The data of integrated circuits are transmitted via I/O buffers according to the requirements of interfaces. With advancement of semiconductor manufacturing process, specifications of transmission interfaces such as supply voltage and output slew rate become more stringent than ever. This thesis proposes "a mixed-voltage output buffer with PVTL compensation", and "a mixed-voltage I/O buffer with slew rate compensation".

The first topic of the thesis is "a mixed-voltage output buffer with PVTL compensation". To transmit data with various voltage levels, the output stage consists of stacked MOSFETs such that the gate-oxide overstress would be avoided. To reduce the variation of the output slew rate, novel PVT variation detectors are proposed. They can detect the PVT corners of PMOS and NMOS at the same time. In addition, the transient current of the output stage is reduced by a proposed leakage current compensation mechanism. The improvement of slew rate is verified on silicon to be 22%.

The second topic is "a mixed-voltage I/O buffer with slew rate compensation". The I/O buffer can transmit and receive data bits determined by the input signal. The PVT variation detectors are also employed in this design to improve the performance. The error of process corner detection is reduced and the improvement of slew rate is justified to be 38.3% by simulations.

[論文審定書+i]
[誌謝+ii]
[論文摘要+iii]
[Abstract+ iv]
[目錄+v]
[圖次+ix]
[表次+xii]
[1 概論+1]
[1.1 前言+1]
[1.2 相關文獻與研究探討+5]
[1.2.1 混合電壓輸入輸出緩衝器+5]
[1.2.2 製程、電壓及溫度變異偵測器+8]
[1.3 研究動機+10]
[1.4 論文大綱+10]
[2 具製程、電壓、溫度以及漏電流補償之混合電壓輸出緩衝器+12]
[2.1 簡介+12]
[2.2 電路架構+13]
[2.3 輸出緩衝器設計+14]
[2.3.1 前置驅動電路+16]
[2.3.2 Vg2 產生電路+17]
[2.3.3 Vg1 產生電路+18]
[2.3.4 輸出級+20]
[2.4 製程、電壓、溫度與漏電流補償電路設計+ 24]
[2.4.1 P-PVT 變異偵測器+24]
[2.4.2 N-PVT 變異偵測器+29]
[2.4.3 回授電路+31]
[2.4.4 數位邏輯電路+32]
[2.5 電路模擬與預計規格+33]
[2.5.1 PVTL 補償模擬+34]
[2.5.2 最高資料速率模擬+35]
[2.5.3 預計規格+36]
[2.6 晶片佈局與量測+36]
[2.6.1 晶片佈局+37]
[2.6.2 量測環境與設定+38]
[2.6.3 晶片量測+39]
[2.7 結果與討論+40]
[3 具電壓迴轉率補償之混合電壓輸入輸出緩衝器+43]
[3.1 簡介+43]
[3.2 電路架構+43]
[3.3 輸入輸出緩衝器設計+45]
[3.3.1 前置驅動電路+47]
[3.3.2 Vg2 產生電路+47]
[3.3.3 Vg1 產生電路+48]
[3.3.4 輸出級+49]
[3.3.5 輸入級+49]
[3.4 製程、電壓、溫度與漏電流補償電路設計+50]
[3.4.1 P-PVT 變異偵測器+51]
[3.4.2 N-PVT 變異偵測器+52]
[3.4.3 數位邏輯電路+54]
[3.5 電路模擬與預計規格+55]
[3.5.1 PVTL 補償模擬+56]
[3.5.2 傳輸模式之最高資料速率模擬+ 57]
[3.5.3 接收模式之最高資料速率模擬+58]
[3.5.4 預計規格+59]
[3.6 晶片佈局與量測+59]
[3.6.1 晶片佈局+60]
[3.6.2 量測考量+60]
[3.7 結果與討論+61]
[4 結論與未來研究方向+62]
[4.1 具製程、電壓、溫度以及漏電流補償之混合電壓輸出緩衝器+62]
[4.2 具電壓迴轉率補償之混合電壓輸入輸出緩衝器+63]
[參考文獻+66]

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