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論文名稱 Title |
具製程電壓溫度偵測與迴轉率補償之混合電壓輸出緩衝器 Mixed-Voltage Output Buffer with Process, Voltage, and Temperature Detectors for Slew Rate Compensation |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
95 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2015-06-29 |
繳交日期 Date of Submission |
2015-07-09 |
關鍵字 Keywords |
迴轉率、輸出緩衝器、高速、互補式金屬氧化物半導體、歪斜反相器、角落 corner, skew inverters, slew rate, output buffer, high operating speed, complementary metal-oxide-semiconductor |
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統計 Statistics |
本論文已被瀏覽 5675 次,被下載 0 次 The thesis/dissertation has been browsed 5675 times, has been downloaded 0 times. |
中文摘要 |
今日之許多數位傳輸工具已應用互補式金屬氧化物半導體製程實現,以滿足人類需求,例如通用序列匯流排、藍牙和音頻播放器等。互補式金屬氧化物半導體製程提供了積體電路高速、低功率和面積小等優點。然而,當互補式金屬氧化物半導體製程越來越先進,使得其特性容易隨製程飄移、電壓飄移和溫度飄移等因素而變動。因此,本論文提出了製程、電壓和溫度補償技術,可應用於兩倍操作電壓輸出緩衝器,解決前述問題。 本論文首先介紹具迴轉率補償之兩倍操作電壓輸出緩衝器,其中提出一製程、電壓和溫度感測器,以監控兩倍操作電壓輸出緩衝器角落狀態,再藉由後端的製程、電壓和溫度判斷器進行角落判斷,其製程、電壓和溫度判斷器根據角落狀態,選擇導通兩倍操作電壓輸出緩衝器中不同的電流路徑以補償迴轉率。 同時,本論文亦提出另一製程角落檢測方法,係利用歪斜反相器之組合,亦可應用於兩倍操作電壓輸出緩衝器。 前述製程角落檢測之歪斜反相器利用不同的歪斜的反相器實現,因為不同的歪斜反相器提供不同的轉態點,可以分辨不同製程角落。其偵測的角落狀態傳遞至後端的製程、電壓和溫度判斷器,該製程、電壓和溫度判斷器則根據製程、電壓和溫度角落,選擇導通兩倍操作電壓輸出緩衝器中不同的電流路徑以補償迴轉率。 本論文所提出之設計均以互補式金屬氧化物半導體製程實現,實際量測證明本論文提出之技術可以針對迴轉率改善至少6%,最高可達26%。 |
Abstract |
Many digital devices such as universal serial bus, bluetooth, and digital audio player have been widely used in human daily life. Nanoscale complementary metal-oxide-semiconductor (CMOS) technology to realize these devices undoubtedly provides many advantages, such as high operating speed, low power consumption, and small area for system-on-chip integration. However, problems associated with advanced nanoscale CMOS technology such as process, voltage, and temperature variations will become devastating in the technology evolution. Thus, this thesis proposes the process, voltage, and temperature compensation technologies, which can be applied to nanoscale CMOS, particularly, 2xVDD output buffers. A 2xVDD output buffer with a PVT detector for slew rate compensation is firstly introduced. The proposed PVT sensor is used to detect PVT corners of the buffer.According to the detected PVT corners, the PVT decision circuit turns on different current paths within the 2xVDD output buffer to compensate for the slew rate. Furthermore, the proposed design implemented by 1xVDD devices attains 2xVDD output range. Particularly, process corner sensors consisting of skew inverters for the 2xVDD output buffer are also investigated. The proposed process sensors take advantage of different transfer characteristics of skew inverters to separate the p-type and n-type MOS’s F and S corners. According to the detected PVT corners, the PVT decision circuit correspondingly turns on different current paths within the 2xVDD output buffer to compensate for the slew rate. Finally, the proposed 2xVDD output buffers are implemented using CMOS processes to justify their performance. Notably, the slew rate is significantly improved when the 2xVDD output buffer is supported by a PVT sensor for slew rate compensation and skew inverters for process corner detection. The maximum slew rate improvements are 26% and 8%, respectively, justified by physical measurements. |
目次 Table of Contents |
[論文審定書+i] [誌謝+iii] [中文摘要+iv] [Abstract+v] [List of Figures+ix] [List of Tables+xiii] [Chapter 1 Introduction+1] [1.1 Motivation+1] [1.1.1 Digital Devices+1] [1.1.2 Problem Definition+2] [1.1.3 CMOS MOS Basics+3] [1.2 Literature Review+6] [1.2.1 Prior Mixed-voltage I/O Buffer Designs+6] [1.2.2 Prior PVT Sensor Designs+8] [1.2.3 Prior PVT Compensation Methods+10] [1.3 Organization of the Thesis+11] [Chapter 2 2xVDD Output Buffer with PVT Detector for Slew Rate Compensation+12] [2.1 Overview+12] [2.2 2xVDD Output Buffer Architecture+12] [2.2.1 PVT sensor+13] [2.2.2 PVT decision circuit+19] [2.2.3 2xVDD output buffer+19] [2.3 Implementation and Measurement+23] [2.4 Summary+27] [Chapter 3 Process Corner Detection by Skew Inverters for 2xVDD Output Buffer+28] [3.1 Overview+28] [3.2 Process Corner Detection Architecture Using Skew Inverters for 2xVDD Output Buffer+28] [3.2.1 PVT Sensor+29] [3.2.2 PVT Decision Circuit+42] [3.2.3 2xVDD Output Buffer+43] [3.3 Implementation and Measurement+44] [3.4 Summary+48] [Chapter 4 Conclusion and Future Work+49] [4.1 Conclusion+49] [4.2 Future Work+50] [References+53] [Appendix A: uncompensated and compensated measurement results+62] [Appendix B: uncompensated and compensated eye diagrams+70] [Appendix C: uncompensated and compensated measurement results+74] [Appendix D: uncompensated and compensated eye diagrams+78] |
參考文獻 References |
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