本論文包含兩個研究主題，分別提出電池管理系統所需之高壓資料傳送電路，以及補償靜態隨機存取記憶體之讀取迴轉率的方法。

第一個主題為可應用於電池管理系統之低功率跨域高壓資料傳送電路，其系統標的為一13串電池芯的電動摩托車之電池管理系統，電池模組電壓範圍為36.4 V ~ 54.6 V。在前述系統中，電池互連模組的電池相關資訊可傳至低壓側之電源管理系統，以進行管理與分析。為了解決高壓系統與低壓系統間之數位資料傳輸問題，本論文提出一個新的電路架構，包含高壓到低壓之資料傳送電路及低壓到高壓之資料傳送電路，且不使用任何的隔離元件，且功率消耗低及面積小等優點。此一設計是使用台積電TSMC 0.25 μm CMOS High Voltage Mixed Signal General Purpose IIA based BCD製程實現，其量測結果的功率消耗為0.425 mW/Mbps，傳輸延遲為1.9 us，資料傳輸速率為0.32 Mbps。

第二個主題為補償讀取迴轉率之5T靜態隨機存取記憶體，係提出以一補償電路加入到先前研發之單端讀寫無擾動5T無負載式靜態隨機存取記憶體中，以兩個相同1 k位元的記憶體陣列來展現其讀取補償電路的效能。當靜態隨機存取記憶體於低電壓時，由自我調適電壓偵測器開啟提升字元線電壓之電路，將提升電壓後的字元線對記憶體單元進行補償。此一設計是使用台積電TSMC 28 nm CMOS LOGIC Low Power ELK Cu 1P10M製程實現，其佈局後模擬結果平均改善27.077%的讀取迴轉率與13.694%的功率消耗。

This thesis consists of two research topics, i.e., a high-voltage data transmitter for Battery Management Systems (BMS) and an SRAM with readout slew-rate compensation.

The first topic demonstrates a low power cross-domain high-voltage transmitter for BMS. The design is aimed at applications to a 13-cell string in E-scooters's BMS. The voltage range of the battery string is from 36.4 V to 54.6 V. The individual battery information is expected to be transmitted to the low voltage side where the BMS will carry out the management and analysis. To resolve the voltage level unmatching issue in digital data between a high voltage domain and a low voltage domain, a novel circuit design consisting of high to low transmitters and low to high transmitters is proposed. The advantages of the proposed transmitters are low power dissipation, small area, and no need of any isolator. Measurement results on silicon using TSMC 0.25 μm CMOS High Voltage Mixed Signal General Purpose IIA based BCD process justify that the power dissipation is 0.425 mW/Mbps, and the propagation delay is 1.9 us.

A 5T SRAM with readout voltage slew-rate compensation is proposed in the second part. When the supply voltage is low, an adaptive voltage detector will switch on the word-line boosting circuit to compensate the readout for the single-ended disturb-free 5T load-less SRAM. Post-layout simulations based on implementation using TSMC 28 nm CMOS LOGIC Low Power ELK Cu 1P10M process demonstrate that the readout slew-rate is enhanced by 27.077%, and the average power dissipation is reduced by 13.694%.

[論文審定書+ i]
[論文公開授權書+ ii]
[中文摘要+ iii]
[英文摘要+ iv]
[目錄+ v]
[圖次+ viii]
[表次+ xii]
[1 概論+1]
[1.1 前言+ 1]
[1.2 相關研究與文獻探討+ 7]
[1.2.1 電池管理系統傳輸+7]
[1.2.2 靜態隨機存取記憶體與補償方式+12]
[1.3 研究動機+ 16]
[1.4 論文大綱+16]
[2 低功率跨域高壓資料傳送器+ 17]
[2.1 簡介+ 17]
[2.2 高壓資料傳送器整體架構+ 18]
[2.3 高壓資料傳送器電路設計+ 19]
[2.3.1 低壓到高壓資料傳送器+ 19]
[2.3.2 高壓到低壓資料傳送器+ 22]
[2.3.3 參考電流源+ 25]
[2.3.4 鎖存資料電路+27]
[2.4 電路模擬與預計規格+ 28]
[2.4.1 晶片設計與佈局+28]
[2.4.2 高壓傳送器佈局後模擬結果與分析+ 29]
[2.4.3 預計規格與效能比較+ 32]
[2.5 晶片實作與量測結果+ 34]
[2.5.1 晶片量測結果與分析+ 36]
[2.5.2 預計規格與實測結果+ 38]
[2.6 結果與討論+ 40]
[3 補償讀取迴轉率之5T 靜態隨機存取記憶體+ 41]
[3.1 簡介+ 41]
[3.2 補償讀取迴轉率之5T SRAM 架構+ 41]
[3.3 補償讀取迴轉率之5T SRAM 電路設計+ 43]
[3.3.1 單端無擾無負載式之5T SRAM 單元+ 43]
[3.3.2 行解碼器與列解碼器+ 45]
[3.3.3 補償讀取迴轉率電路+ 46]
[3.3.4 內建自我測試電路+ 49]
[3.4 電路佈局後模擬+ 51]
[3.4.1 晶片設計與佈局+ 51]
[3.4.2 SRAM cell 模擬+ 52]
[3.4.3 SRAM 系統模擬+ 54]
[3.5 預計規格與效能比較+ 59]
[3.6 結果與討論+ 60]
[4 結論與未來規劃+61]
[4.1 論文貢獻+ 61]
[4.2 未來研究方向+ 61]
[參考文獻+ 65]

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