本論文探討兩個研究主題，分別為單端讀寫且無擾動的5T無負載式4Kb靜態隨機存取記憶體，及記憶體所需的漏電流偵測電路與補償電路。

第一個主題為單端讀寫且無擾動的5T無負載式4Kb靜態隨機存取記憶體，其係以五個電晶體組成的無負載式記憶體單元構成，具有字元控制器、單端讀寫功能和寫入輔助迴圈的設計，可以有效地隔絕外部雜訊，因而記憶體單元可操作於低電壓且不受雜訊干擾。另外，位於反位元線和位元線之間的共享式反相器，不僅能隔絕記憶體單元和位元線的雜訊，更可以由多個記憶體單元共用，將記憶體的面積間接成本(Overhead cost)降到最低。此記憶體所內建的自我測試電路，可進行測試模式的讀取與寫入，以瞭解記憶體的讀取與寫入功能是否正常。本電路以量測結果正規化之後與現有靜態隨機存取記憶體技術相較，減少6.53%的面積成本，且功率下降50.99 %。

第二個主題提出一漏電流偵測電路及補償電路，由記憶體單元模型、參考電壓電路、比較器電路和漏電流補償電路組成，並實現於前述的單端讀寫且無擾動之5T無負載式1Kb靜態隨機存取記憶體。當記憶體單元的漏電流足以影響存取結果的時候，漏電流偵測電路會發送一警訊，喚起漏電流補償電路，以達到降低功率消耗、減少讀取延遲時間的目標。本電路以正規化模擬數據與現有之靜態隨機存取記憶體技術比較，平均可改善36.68 %之讀取延遲時間、減少27.86 %之功率消耗，而付出7.48 %的面積成本代價。

This thesis consists of two topics, including a single-ended disturb-free 5T load-less 4Kb SRAM, and the leakage current sensor and compensation circuit mainly designed for memories, e.g., the mentioned single-ended disturb-free 5T load-less SRAM.

The first topic presents a single-ended disturb-free 5T load-less 4Kb SRAM. The single-ended load-less SRAM cell consist of 5 transistors, where a write assistant loop and an isolated wordline-controlled transistor (WLC) are integrated therewith. The proposed cell is proved to attain the smallest area and disturb-free during the memory access. A shared bitline inverter is included to boost the read access speed at the minimal expense of area cost. Furthermore, a build-in self-test (BIST) circuit is included in the memory for testable R/W access. Based on the on-silicon measurements, the proposed 5T 4Kb SRAM shows superior performance in terms of power per access after normalization of the technology parameters.

The second topic discloses a leakage current sensor and compensation circuit, consisting of a SRAM cell model, a reference voltage circuit, a comparator and the compensation circuit. The circuit is implemented in the mentioned single-ended disturb-free 5T load-less 1Kb SRAM. When the leakage current seriously endangers the state of the data bit, the sensor will notify a warning message to the compensation circuit and wake it up to refresh the corresponding bit. This circuit is proven to reduce 27.86% of the power consumption and boost 36.68 % of the speed during read access based on all-PVT-corner post-layout simulations results.

摘要 i
Abstract ii
目錄 iii
圖次 v
表次 viii
第一章 概論 1
1.1 前言 1
1.2 靜態隨機存取記憶體相關介紹 3
1.2.2 雜訊邊際 3
1.2.3 無負載式4T靜態隨機存取記憶體單元 5
1.3 相關文獻與研究討論 9
1.3.1 靜態隨機存取記憶體單元 9
1.3.2 漏電流偵測與補償電路 14
1.4 研究動機 16
1.5 論文大綱 16
第二章 單端讀寫無擾動5T無負載式4Kb靜態隨機存取記憶體 17
2.1 簡介 17
2.2 5T無負載式靜態隨機存取記憶體之電路架構 17
2.3 5T無負載式靜態隨機存取記憶體之子電路設計 19
2.3.1 5T無負載式靜態隨機存取記憶體單元 19
2.3.2 行架構 22
2.3.3 行解碼器與列解碼器 25
2.3.4 控制電路 27
2.3.5 內建自我測試電路 27
2.4 電路模擬與預計規格 29
2.4.1 記憶體單元模擬分析 29
2.4.2 記憶體電路模擬分析 33
2.4.3 預計規格與效能比較 35
2.5 晶片佈局 37
2.6 晶片實作與測量結果 38
2.6.1 晶片量測結果與分析 39
2.6.2 預計規格與實測結果 42
2.7 結果與討論 45
第三章 記憶體的漏電流偵測及補償電路 46
3.1 簡介 46
3.2 漏電流偵測及補償電路架構 47
3.3 漏電流偵測及補償電路設計 47
3.3.1 靜態隨機存取記憶體單元模型 47
3.3.2 參考電壓電路 48
3.3.3 比較器電路 50
3.3.4 漏電流補償電路 52
3.4 電路模擬與效能比較 53
3.4.1 漏電流偵測及補償電路模擬結果 53
3.4.2 效能比較 56
3.5 晶片佈局 57
3.6 結果與討論 59
第四章 結論與未來工作 60
參考文獻 64

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