本論文提出了一個解析度為十位元的類比數位轉換器，取樣頻率為一億赫茲(100MHz)，設計上，為了提升轉換速度，高位元轉換的部分採用一次二位元轉換，但因為需使用三個比較器，所以提高了發生錯誤的機率，因此本篇架構在高位元的部分使用了非二進制校正技術來容許錯誤發生並修正錯誤；在低位元轉換的部分則使用一次一位元轉換以增加精確度，此外，為了可以進一步提升效率，低位元轉換的部分採用了輪替技術，除了可以更有效率地使用比較器之外，也可以緩解低位元比較時間較長的問題，最後，在低位元的部分加入了一個冗餘位元以增加低位元的容錯能力。
本論文實現了一個一億次取樣率的十位元類比數位轉換器，採用TSMC 90nm製程技術，靜態分析上，其DNL為+1.248 / -0.750 LSB，INL為+1.679 / -1.677 LSB，動態分析上，SFDR與SNDR在尼奎斯特頻率下分別為62.76 dB和56.099 dB，有效位元為9.026 bit，功率消耗為2.397 mW，FoM為45.98 fJ/conv.-step。

In this thesis, a 10-bit resolution analog-to-digital converter with 100MHz sampling frequency is proposed. In terms of design, in order to improve the conversion speed, the 2b/cycle conversion is adapted in the conversion of the upper bits. Since three comparators are required to perform the 2b/cycle conversion, it may cause the increase of the error probability. Therefore, the proposed architecture adapts the non-binary correction technique in the upper bits to tolerate fault error and hence correct the error. In the lower bit conversion, a 1b/cycle conversion is implmented to increase the accuracy. Moreover, the architecture also adopted the alternate technique in lower bit conversion to improve the conversion efficiency. This technique not only uses the comparators more efficiently, but also relaxing the issue of the longer comparison time in the lower bit conversions. At last, a redundant bit is added in the lower bits to increase the fault tolerance capability of the lower bits.
This thesis implements a 10-bit analog-to-digital converter with 100MHz sampling frequency by using the TSMC 90nm process technology. For the static analysis, the DNL and INL are +1.248 / -0.750 LSB and +1.679 / -1.677 LSB, respectively. For the dynamic analysis, the SFDR and SNDR at the Nyquist rate are 62.76 dB and 56.099 dB. The ENOB is 9.026 bit, the power consumption is 2.397 mW and FoM is 45.98 fJ / conv.-step.

目錄
論文審定書 i
中文摘要 ii
Abstract iii
目錄 iv
圖目錄 viii
表目錄 xi
Chapter 1. 緒論 1
1.1 背景 1
1.2 研究動機與目標 2
1.3 論文章節組織 2
Chapter 2. 基本架構及相關技術介紹 4
2.1 類比數位轉換器(Analog to Digital Converter) 4
2.2 連續漸進式類比數位轉換器(The Successive Approximation ADC) 6
2.2.1. 一次一位元轉換連續漸進式類比數位轉換器 6
2.2.2. 一次兩位元轉換 9
2.2.3. 一次一位元輪替轉換 11
2.2.4. 各轉換技術之優缺點比較 12
2.3 數位校正技術 13
2.3.1. 非二進制數位校正技術 13
2.3.2. 冗餘位元數位校正技術 13
Chapter 3. 目標架構電路介紹與分析 15
3.1 設計考量 15
3.2 取樣保持電路 (Sample & Hold) 15
3.2.1. 取樣開關之導通電阻考量 16
3.2.2. 傳統拔靴帶式開關(Bootstrapped Switch) 18
3.2.3. 改良型拔靴帶式開關 19
3.3 MOS開關 22
3.3.1. 電荷注入效應(Charge Injection) 22
3.3.2. 時脈耦合效應(Clock Feedthrough) 23
3.4 比較器設計 24
3.4.1. 反饋雜訊(Kick-Back Noise) 25
3.4.2. 全差動式動態比較器 27
3.5 電路輸出端驅動能力 28
Chapter 4. 目標類比數位轉換器之實現 30
4.1 整體架構 30
4.2 時脈產生電路 33
4.2.1. 占空比時脈產生器 (Duty Cycle Clock Generator) 33
4.2.2. 非重疊時脈產生器 (Non-overlapping Clock Generator) 35
4.3 電容陣列數位類比轉換器 36
4.3.1. 訊號電容陣列比例及開關操作 36
4.3.2. 參考電壓電容陣列比例及開關操作 38
4.4 非同步控制電路 41
4.5 解碼電路 44
4.5.1. 比較結果轉非二進制碼 44
4.5.2. 數位取代電路 45
4.5.3. 非二進制碼轉二進制碼 46
4.6 類比數位轉換器全電路電路佈局 48
4.7 佈局後之電路調整 49
4.7.1. 電容陣列失真 49
4.7.2. 比較器偏移(Offset) 51
Chapter 5. 效能與模擬結果分析 52
5.1 類比數位轉換器之特性指標 52
5.2 靜態效能(Static Performance) 52
5.2.1. 微分非線性誤差(DNL) 52
5.2.2. 積分非線性誤差(INL) 53
5.3 動態效能(Dynamic Performance) 53
5.3.1. 訊號雜訊比(Signal-to-Noise Rate) 54
5.3.2. 訊號雜訊失真比(Signal-to-Noise &Distortion Rate) 54
5.3.3. 無雜散動態範圍(Spurious-Free Dynamic Range) 55
5.3.4. 有效位數(Effective Number of Bits) 55
5.4 模擬結果 56
5.4.1. 靜態分析 56
5.4.2. 動態分析 58
5.5 規格對照表 59
Chapter 6. 結論與未來展望 61
6.1 結論 61
6.2 未來展望 61
References 63

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