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博碩士論文 etd-0614101-164407 詳細資訊
Title page for etd-0614101-164407
論文名稱
Title
在記憶體處理器系統上改善工作負載平衡與程式最佳化
Improving Workload Balance and Code Optimization on Processor-In-Memory Systems
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
52
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2001-05-29
繳交日期
Date of Submission
2001-06-14
關鍵字
Keywords
輪次、記憶體處理器、陳述
statement, PIM, iteration
統計
Statistics
本論文已被瀏覽 5685 次,被下載 1972
The thesis/dissertation has been browsed 5685 times, has been downloaded 1972 times.
中文摘要
記憶體處理器(Processor-In-Memory)是在最近幾年中被提出,它主要的目的在於減少記憶體與處理器間效能的差距,在過去,我們為了能利用記憶體處理器潛在的優點,提出了一種以陳述(Statement)作為分析模型的平行系統-SAGE[1,2]。在這篇論文中,為了使記憶體處理器中的各個處理器能有最適量的工作,以輪次(Iteration)為目標的分析方法為另一個重要的研究概念,我們設計出幾種最佳化技巧去擴展原有系統的效能,這些技巧包含了智慧型記憶體操作辨識法(IMOP; Intelligent Memory Operation Recognition)、PIM式的分塊法(Tiling)與一個能取得精確工作分配(Workload Balance)的執行流程;最後,我們將提出我們的實驗結果,並且對這些結果做一個討論。
Abstract
PIM (Processor-In-Memory) architectures have been proposed in recent years. One major objective of PIM is to reduce the performance gap between the CPU and memory. To exploit the potential benefits of PIM, we designed a statement base parallelizing system –SAGE in [1, 2]. In order to make all processors take the best-fit workload in PIM, iteration base analysis is another research issue in this paper. We extend this system to achieve better performance by devising several comprehensive optimizing techniques, which include IMOP (Intelligent Memory Operation) recognition, tiling for PIM, and a precise mechanism to get workload balance execution schedule. The experimental results are also presented and discussed.
目次 Table of Contents
目錄

中文摘要...................................................I
英文摘要..................................................II
目錄.....................................................III
圖目錄.....................................................V
表格與演算法目錄.........................................VII
第一章 介紹................................................1
第二章 智慧型記億體之架構..................................6
第2.1節 智慧型記憶體(IRAM) ................................6
第2.2節 動態頁(Active Page)................................7
第2.3節 資料集中式架構(DIVA) ..............................9
第2.4節 FlexRAM架構描述...................................10
第2.5節 基本參數..........................................11
第三章 平行的方法.........................................13
第3.1節 加權分割圖的建立..................................14
第3.2節 加權時間自我修補法................................16
第3.3節 PIM式的分塊法.....................................21
第3.4節 在記憶體處理器架構下的迴圈分割....................23
第3.5節 智慧型記憶體操作辨識法............................25
第3.6節方法整合...........................................31
第四章 實驗結果...........................................32
第五章 結論...............................................36
參考文獻 References
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9. Granacki, J. et al. Data Intensive Architecture: DIVA. http://www.isi.edu/asd/diva/, (1998).
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11. Jiménez, M.: Multilevel Tiling for Non-Rectangular Iteration Spaces. Ph.D. Thesis, Departamento de Arquittectura de Computadores, Universitat Politécniac de Catalunya, May (1999).
12. Yoo, S. M., Renau, J., Huang, M., and Torrellas, J.: FlexRAM Architecture Design Parameters. Technical Report 1584, Oct. (2000).
13. Veenstra, J., and Fowler, R.: MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors. In MAS-COTS’94, Jan. (1994), pp. 201-207.
14. Judd, D., and Yelick, K.: Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler. In proceedings of 2nd Workshop on Intelligent Memory Systems, Cambridge, MA, Nov. 12, (2000).
15. Moritz, C. A., Frank, M., and Amarasinghe, S.: FlexCache: A Framework for Flexible Compiler Generated Data Caching. In proceedings of 2nd Workshop on Intelligent Memory Systems, Cambridge, MA, Nov. 12, (2000).
16. Veidenbaum, A. V., Tang, W., Gupta, R., Nicolau, A., and Ji, X.: Adapting cache line size to application behavior. In Proceedings ICS'99, Jun. (1999).
17. Press, W. H., Teukolsky, S. A., Vetterling, W. T., and Flannery, B. P.: Numerical Recipes in Fortran 77. Cambridge University Press, (1992).
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