本論文分為三個部分：第一部份為快速管線式前瞻進位加法器設計與實作；第二部份為介紹如何在Cadence97環境下，自己建立0.35μm制程的元件庫，並進行cell-based流程；第三部份為低功率離散餘弦轉換之設計與實作。
第一部份在論文中我們所提出的32位元樹狀架構管線式之前瞻進位加法器是使用全N型電晶體 (簡稱ANT) 電路元件所設計的。這種加法器不僅只需極少的電晶體數目，而且使用較少晶片面積。此外，以TimeMill的模擬軟體做32位元加法器的佈局後模擬結果，操作時脈的速度可以達到1.25 GHz。以這個架構而言，也可以容易擴充資料長度。
第二部分是針對如何在Cadence97環境下自行建構的元件庫的流程作一完整的說明，並對如何利用自己所建立的元件來完成cell-based的流程及其應該注意的事項加以解釋。
第三部份為離散餘弦轉換之設計與實作。針對運算單元—乘法累加器 (MAC) 的運算做觀察，改良其運算方式以減少功率消耗。

The thesis comprises three parts: Part 1 is the design and implementation of a high speed pipelined carry lookahead adder (CLA) ; Part 2 introduces how to build 0.35μm basic cell library in the Cadence 97’s environment and execute the cell-based design flow by self-built basic cells; Part 3 is the design and implementation of a low-power discrete cosine transform (DCT) processor.
Part 1 of this thesis is a 32-bit tree-structured pipelined carry lookahead adder (CLA) constructed by the modified all-N-transistor (ANT) design. Not only the CLA possesses few transistor count, but also occupies small chip size. Moreover, the post- layout simulation results given by TimeMill show that the clock used in the 32-bit CLA can run up to 1.25 GHz. The proposed architecture can be easily expanded for long data addition.
Part 2 of this thesis is to describe the procedure of a self-built cell library in detail, and explain how to correctly proceed cell-based design flow by using the self-built basic cell library.
Part 3 of this thesis is to implementation of a DCT processor. We carefully observed the operation behavior of Multiply Accumulator (MAC) and improved the power consumption

目錄

摘 要 i
Abstract ii
第一章 簡介 1
1.1 研究動機 1
1.2 論文目的 2
1.3 論文大綱 3
第二章 樹狀結構之前瞻式進位加法器 4
2.1 概論 4
2.2 原理與架構說明 4
2.2.1 All-N-Transistor (ANT) 模組元件 5
2.2.1.1 電晶體長寬比的問題 7
2.2.2 Generate及Propagate 模組單元 7
2.2.3 Carry-lookahead generator 模組單元 9
2.2.4 Sum generator 模組單元 11
2.3 速度與面積的分析 13

2.3.1 速度分析 13
2.3.2 面積分析 13
2.4 效能的比較 14
2.5 加法器的模擬與實作 15
2.5.1 設計流程 15
2.5.2 測試考量 16
2.5.2.1時脈產生電路 16
2.5.2.2測試向量產生電路 18
2.5.3 整體電路方塊圖 19
2.5.4 佈局模擬結果 20
2.5.5 晶片佈局 21
2.5.6 量測結果 23
2.5.6.1 八位元CLA量測 23
2.5.6.2 三十二位元CLA量測 25
2.6 結論 26
第三章 自建基本元件 27
3.1動機 27
3.2 流程簡介 27
3.3 環境設定 28
3.4 建構基本元件 29
3.4.1 高度考量 30
3.4.2 腳位配置 31
3.4.3 邊界設定 33
3.4.4 圖層 (layer) 設定 33
3.4.5 結論 35
3.5 產生萃取圖 35
3.5.1 修改設定 36
3.5.2 啟動Flow Sequencer視窗 37
3.5.3 設定選項 38
3.5.4 萃取圖的修改 41
3.5.5 產生blackbox，spi及hcell 41
3.6 程式撰寫技巧 42
3.7 銲接點 (PAD) 的配置 43
3.8 Silicon Ensemble (SE) 的流程 43
3.8.1 Create Library的注意事項 43
3.8.2 Verilog In 的注意事項 44
3.8.3 SE工作環境設定的注意事項 45
3.8.4 SE Follow pin的注意事項 45
3.8.5 Dracula驗證的注意事項 46
3.9 佈局後的模擬 (Post Layout Simulation) 46
3.9.1 HSPICE 46
3.9.2 TimeMill/PowerMill 46
第四章 離散餘弦轉換 (DCT) 47
4.1概論 47
4.2 架構簡介 47
4.3 晶片的合成與佈局 51
4.3.1 合成結果 51
4.3.2 佈局結果 52
4.4 晶片的模擬 53
4.4.1 功能驗證 53
4.4.2 效能比較 55
4.5 結論 55
第五章 結論 55
參考文獻 56
附錄 58
附錄一 (以八位元為例) 58
附錄二 (dct.script) 65

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