在論文中的第一部分我們提出一個高速的時脈產生電路，其具有負延遲的功能，並且可以解決多重鎖定的問題，如果將此電路應用記憶體的時脈產生電路時，將具有省電及快速存取的功能，同時也可快速的鎖定訊號。當所用的製程為台灣積體電路製造股份有限公司(TSMC) 所提供的0.35um CMOS 1P4M時，此電路可在輸入雜訊為 10% 時的1.0 GHz 時脈下動作。

　　第二部分是研發出與 Sony PlayStation 二代主機相容之搖桿擴充介面 (Sony 原廠之產品取名為Multitap)，此介面可使一個主機搖桿插槽同時使用四支搖桿，因主機有二個搖桿插槽，所以配合此介面，最多可同時使用八支搖桿。

　　The first topic of this thesis is a high-speed digital clock generator circuit is presented to provide negative delays in order to avoid a multi-locking hazard. The negative delay also results in small power consumption and shorter access time if the proposed circuit is used in the clock generator circuit of memory devices. Meanwhile, an accurately locked clock signal is also provided. The locked clock signal can be as high as 1.0 GHz at the presence of a random noise with 10% of power supply voltage when the design is implemented by TSMC (Taiwan Semiconductor Manufacturing Company) 0.35um CMOS 1P4M technol- ogy.


　　The second topic of this thesis is an 1-to-4 joystick enhanced interface which can be attached to SONY PS2 (playstation 2) is developed. The enhanced interface can allow 4 persons to play simultaneously through one port at the original game console. A total of 8 players can be supported when two of the interfaces hook up with both joystick ports of the console. The multiple player entertainment effect can be drastically enhanced by the usage of such an interface.

目錄

摘要………………………………………………..i
Abstract…………………………………………..ii
第一章 簡介……………………………………...1
1.1 研究動機與目的 1
1.2 先前相關文獻研究 2
1.3 論文大綱 3
第二章 使用單擊鎖定方法之具負延遲1.0 GHz時脈產生器……………………………..4
2.1 概論 4
2.2 架構簡介 5
2.2.1 負延遲時脈之動作原理 5
2.2.2單擊鎖定之架構說明 7
2.2.3 負延遲之計算 9
2.3 模擬結果 10
2.4 測試結果 13
2.5 結論 15

第三章 Sony Playstation 二代搖桿一對四介面之實現…………………………………16
3.1 概論 16
3.2 架構簡介 17
3.2.1 記憶卡訊號的編解碼 17
3.2.2 搖桿訊號的編解碼 21
3.2.3 搖桿選擇 24
3.2.4 擴充介面認可 26
3.2.5 自動重置 28
3.3 實作與驗證 30
3.3.1 訊號量測 30
3.3.2 FPGA 實作 36
3.3.3 實作測試 38
3.4 結論 40
第四章 總結……………………………………41
參考文獻………………………………………...42
附錄……………………………………………..44

參考文獻

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