非揮發性記憶體的資料存取速度介於揮發性記憶體和常規硬碟之間。和揮發性記憶體相比，非揮發性記憶體一經寫入資料，就不需要外界電力來維持其記憶，且其低功耗的特點，更適合作為使用電池的攜帶型電子產品。目前所使用的多晶矽與SONOS結構及近年來發展的奈米點非揮發性記憶體，其儲存層都需長時間的高溫結晶製程，這對產能和製造費用都是一項負擔，因此降低製程溫度是絕對必要的趨勢。
本論文使用Zn與SiO2之非晶混合層，來降低製程溫度，並利用氧化鋅本身缺陷作電荷儲存之浮閘層，來製作奈米薄膜非揮發性記憶體。同時也比對鋅與氧化鋅混合二氧化矽其材料之缺陷特性、電荷儲存能力。超臨界二氧化碳能修補介電層且在高壓環境下降低反應活化能。此外，使用低溫超臨界二氧化碳可成長氧化鋅奈米點的特性，分別對鋅、矽、二氧化矽的組合來形成奈米點，並以鋅與矽共鍍經超臨界處理製做出約180 nm之奈米球。本論文以熱退火方式成功製做出氧化鋅薄膜之非揮發性記憶體，以C-V分析SiO2濺鍍層缺陷，發現以500℃熱退火可消除SiO2之缺陷，而以SiO2/Zn-SiO2/SiO2 結構退火所製做之記憶體元件，在溫度大於700℃時，會因Zn的擴散導致電荷儲存特性消失，因此以熱退火方式來製做記憶體元件必需在500-700℃間來進行。以DLTS分析此儲存層缺陷，發現共鍍Zn-SiO2在退火處理前已有一能階為0.6eV之缺陷，經Ar氣氛退火，則形成一0.47eV之缺陷，而在氧環境下退火後可形成0.85eV之深能階缺陷。以XPS分析，此共鍍層未退火前之缺陷為Zn所造成，經Ar氣氛退火，則轉變成Zn-O-Si為主之型態，而在O2氣氛退火處理後，氧化鋅的含量增加，以C-V量測，有2V之記憶窗戶，顯示此製程所得具有深能階缺陷之儲存層，可以做為電荷儲存之功用。

Non-volatile memory is slower than DRAM (Dynamic Random Access Memory) but faster than HDD (Hard Disk Drive). In addition, compared to volatile memory, the non-volatile memory can retain stored information without power, and consume only low power. These characteristics show its popularity of flash memory built in portable devices. Currently the non-volatile memory applies the polysilicon and SONOS structure as floating gate, however, the new technologies of nanocrystal non-volatile memory are processed at high temperature. The manufacturing cost is rather high, so the process at lower temperature is very necessary. In this work, mixed zinc and silica amorphous layers are applied as floating gate to construct nano thin film non-volatile memory devices. The process does not need high temperature to form crystalline, and the defects in zinc oxide can be applied for charge storage. Supercritical carbon dioxide (SCCO2) treatment has been studied for the passivation of dielectric and reducing the activation energy. Using this low-temperature SCCD process ZnO nanocrystal can be formed, and the feasibility of fabricating nanocrystal NVMs device with low temperature SCCO2 is possible. The nonvolatile memory devices with Zn nano thin film embedded in MIS structure are performed. From C-V measurement, it is found that defects in SiO2 are repaired after 500℃ annealing. Because of the thermal diffusion, the storage layer SiO2/Zn-SiO2/SiO2 in device cannot be observed and the memory window disappears when the annealing temperature is higher than 700℃. Therefore, the annealing process should be performed between 500℃ - 700℃ in making memory device. From DLTS analysis, a species with energy level of 0.6 eV is found in the as deposited Zn-SiO2 layer. After annealing in Ar, a new energy level 0.47 eV is found, and which shifts to energy level 0.85 eV after annealing in O2. In comparison to XPS results, traps of Zn-SiO2 exist before annealing, and after annealing in Ar, Zn-SiO2 transforms into Zn-O-Si. Traps of ZnO-SiO2 have been found after annealing in O2, which increases the memory effect with a 2 Volt memory window, so that more charges can be stored in the deep level traps of ZnO-SiO2 in the storage layer.

目錄
致謝 ............................................. I
中文摘要 ........................................ II
ABSTRACT .................................... III
目錄 ............................................ IV
表目錄 .......................................... VI
圖目錄 ......................................... VII
第一章緒論 .................................... 1
1.1 前言...............................................................................................1
1.2 非揮發性記憶體介紹...................................................................2
1.3 超臨界二氧化碳介紹...................................................................5
第二章能帶理論與深能階暫態能譜原理 .............. 7
2.1 非揮發性記憶體工作原理...........................................................7
2.1.1. 快閃記憶體之寫入與抹除原理............................................................7
2.1.2. 穿隧機制................................................................................................7
2.2 深能階暫態能譜量測原理...........................................................9
2.2.1. Shockley-Read-Hall 復合理論[35] ......................................................9
2.2.2. 脈衝電壓與介面缺陷行為..................................................................12
2.2.3. 缺陷參數決定......................................................................................12
第三章 鋅之非揮發性記憶體元件之製作及分析流程 ... 15
3.1 鋅之非揮發性記憶體元件之製作.............................................15
3.2 深能階暫態頻譜量測.................................................................16
第四章 結果與討論 ............................... 18
4.1 二氧化矽缺陷研究.....................................................................18
4.1.1 退火溫度對二氧化矽缺陷影響..........................................................19
4.1.2 超臨界二氧化碳處理對二氧化矽缺陷影響......................................19
4.2 奈米薄膜儲存特性研究.............................................................20
4.2.1 退火溫度對記憶效應影響..................................................................20
4.2.2 超臨界二氧化碳處理製作奈米點......................................................20
4.2.3 氧對記憶效應影響..............................................................................21
4.3 以深能階暫態頻譜研究缺陷儲存機制.....................................22
第五章結論 ..................................... 25
第六章參考資料 ................................. 26

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