隨著高速數位訊號的演進與電路密度逐年提高，封裝的技術以及繞線的設計有了更高的複雜度，衍生出了許多不可忽視的訊號完整性問題。目前業界的先進封裝技術將多個裸晶組合在一個封裝之內，裸晶之間的連結使用線寬約為2 ~ 4微米的極細線(Fine-line)，先行封裝成FOWLP (Fan-Out Wafer Level Package)架構，再透過FC bump(Flip Chip bump)與傳統線寬25微米之有機基板進行複合式封裝結構。然而當高速數位訊號傳遞於極細線路時，諸多不連續的阻抗特性已不如傳統封裝上可以輕易控制，且因繞線的間距太小所引發的串擾現象，以及極細銅線所產生的導體損耗皆已不能忽略。
本論文探討下一世代100Gbps網通傳輸速度之差分訊號線結構(Differential Signal)之特性與分析，透過特性阻抗、返回損耗(Return Loss)、植入損耗(Insertion Loss)、串擾(Crosstalk)、時域之眼圖(Eye Diagram)與抖動(Jittter)等系統性分析手法提出最佳化的設計準則，並針對極細線路、不連續接面(VIA, FC Bump, Anti-pad, BGA ball)與有機基板電路等各自不同的結構，討論其電氣特性影響。

The rapid development of high-speed digital circuits leads to high complexity of layout design and the accompanying signal integrity problems, and presents a very serious challenge in packaging technology. The state-of-the-art FOWLP (Fan-Out Wafer Level Package) packaging technology assembles 2 to 3 bare chips inside a package using extremely fine lines (2~4 um) linking the chips, the package is then connected to an organic substrate with FC bump or conventional 25 um line to form a hybrid package. However, when high-speed signals travel on the extremely fine line, the impedance characteristics becomes very difficult to control compared to conventional packaging technology. Further, the crosstalk resulting from the extremely close proximity among signal lines and the conductor loss of copper wires due to skin effect are no longer negligible. Moreover, the dielectric loss of the organic substrate and the roughness of the copper line surface all make the design of hybrid packaging even more challenging.
This thesis focuses on the characterization of next-generation 100Gbps differential signal line structures. Effects of factors such as characteristic impedance, line widths, line separations, and roughness of the organic substrate and copper wires on the performance of crosstalk, insertion loss, return loss, eye diagram and jitter are thoroughly investigated to present suggestions on guidelines of optimal designs.

論文審定書 i
致謝 ii
摘要 iii
Abstract iv
目錄 v
圖表目錄 vii
第一章 緒論 1
1.1 研究背景 1
1.2 研究目的與方法 3
1.3 論文大綱 4
第二章 封裝技術之演進與訊號完整性 5
2.1 封裝技術的演進 5
2.2 晶片的整合技術 8
2.3 2.5D IC和扇出型晶圓級封裝 11
2.4 高頻封裝線路之電氣特性 14
2.4.1 有損傳輸線與反射損耗 17
2.4.2 介質損耗與導體損耗 20
2.4.3 串擾效應與差分訊號線 23
第三章 扇出型晶圓級封裝線路之電氣特性 29
3.1 極細線路之傳輸線架構 29
3.1.1極細線路之單端傳輸線特性 29
3.1.2線極細線之差分訊號傳輸線特性 35
3.2扇出型晶圓級封裝之探討 38
3.2.1架構介紹與傳輸線特性之探討 38
3.2.2 FC bump不連續面 44
3.2.3 Anti-Pad不連續面 47
第四章 複合式晶圓級封裝之電氣特性 52
4.1 有機基板線路之探討 52
4.1.1架構介紹及傳輸線特性 52
4.1.2 BGA ball 61
4.2 複合式結構之傳輸線特性 63
4.3 眼圖結果 72
第五章 結論 79
文獻探討 80

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