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博碩士論文 etd-0616113-143150 詳細資訊
Title page for etd-0616113-143150
論文名稱
Title
前瞻顯示器InGaZnO薄膜電晶體之熱載子效應及自我加熱效應物理機制研究
Physical Mechanisms of the Self-Heating and Hot-Carrier Effects on Reliability of InGaZnO Thin Film Transistor for Advanced Displays
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
130
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-24
繳交日期
Date of Submission
2013-08-06
關鍵字
Keywords
熱載子、氧化物半導體、自我加熱、氧化銦鎵鋅、薄膜電晶體
hot-carrier, self-heating, oxide semiconductor, thin film transistor, InGaZnO
統計
Statistics
本論文已被瀏覽 5734 次,被下載 675
The thesis/dissertation has been browsed 5734 times, has been downloaded 675 times.
中文摘要
氧化物半導體薄膜電晶體因為擁有各種有利於顯示器發展之特性,因此近年來吸引了相當多的研究投入,但氧化物半導體薄膜電晶體在實際畫素陣列電路中操作時容易因為操作電壓以及電流而有各種劣化現象,因此本論文探討了氧化銦鎵鋅(InGaZnO)薄膜電晶體於實際操作時可能面臨之熱載子效應及自我加熱效應。實驗結果顯示自我加熱電應力實驗中的汲極偏壓會造成汲極端較多電子捕獲之不對稱劣化情形,且自我加熱效應也會嚴重地造成InGaZnO與閘極氧化層介面的電子捕獲量增加,而臨界電壓偏移量與自我加熱電應力時功率之線性關係驗證了汲極電流所造成的焦耳熱現象。藉由分析溫度效應及其熱活化關係,閘極正偏壓電應力與自我加熱電應力操作時熱場發射之電子捕獲現象所需克服的能障高度皆為相同的,此現象表示汲極偏壓並不會造成額外的劣化因素,而只是增加熱發射量。另外我們也探討了元件尺寸對自我加熱效應的影響,而其影響可歸咎於不同原件尺寸下的散熱效率。從動態操作之自我加熱電應力實驗中可以得出加熱效率會主導其劣化程度,而電流對元件加熱所需之臨界時間也可由此得知,大約為數個毫秒。
在具有雙閘極之接觸窗口型元件,源極和汲極之多餘的電極會屏蔽上閘極所施加的電壓,並造成上閘極施加正偏壓時元件特性曲線只會有開啟電流之上升而不會有臨界電壓減小的情況。另一方面,熱載子效應在具有蝕刻終止層的接觸窗口型元件會造成電子注入到汲極多餘電極下方的通道蝕刻終止層中,而且這些注入的電子會被侷限在多餘電極的位置,這樣的電子注入情形造成閘極-源極電容曲線有兩階段抬升現象,而由汲極多餘電極長度對閘極-源極電容曲線第一階段高度的影響,我們可以知道電容曲線的兩階段抬升是受汲極電極主導。藉由熱載子電應力施加後電容-電壓量測時上閘極偏壓對能帶調變的手法,前述的劣化機制模型得到了驗證。
第三部分我們討論了照光對InGaZnO薄膜電晶體熱載子效應的影響,實驗結果顯示熱載子電應力操作之後靠近汲極端電洞捕獲主導了劣化現象,而不是一般常見的熱載子效應所引發的缺陷產生。雖然此現象對電流-電壓特性曲線沒有明顯的影響,但由電容-電壓量測指出缺陷輔助之光產生電洞會在靠近汲極端被閘極介電層捕獲,此現象是由於源極端與汲極端電場方向不同所導致。進一步分析不同閘極偏壓電應力實驗以及動態操作電應力實驗,我們得知其電洞捕獲現象是與閘極和汲極之間跨壓所決定的,而這也驗證了所提出的閘極-汲極電容曲線劣化的主導機制。
Abstract
Oxide semiconductor thin film transistors have attracted much attention recently since they possess many advantageous properties that are beneficial in the development of displays. However, operation voltage and/or current can lead to device degradation in practical applications. Therefore, the effects of self-heating and hot-carriers in InGaZnO thin-film transistors are investigated in this work. The drain bias during self-heating stress is found to bring about asymmetric degradation, with more electrons trapping near the drain side. Self-heating effect also significantly enhances electron-trapping phenomenon at the InGaZnO/gate insulator interface or within the gate insulator bulk. Drain current-induced Joule heating phenomenon is verified from the relationship between the stress power and threshold voltage shift. From the temperature effect on electron-trapping, the extracted energy barrier height for thermionic-field emission to take place is the same both for positive gate bias stress and self-heating stress, implying that the trapping process is identical and drain bias only plays the role of enhancing thermal emission. The self-heating effect-featured device dimension-dependent degradation is also found in this work, and is attributed to the heat dissipation efficiency. The peculiar degradation behaviors under pulsed self-heating stress elucidates that heating efficiency is the dominant factor influencing the self-heating effect-induced degradation, and the required time for Joule heating to fully take place is estimated to be a few milliseconds.
In via-contact type device with an etch stop layer and dual gate, the redundant source/drain electrodes are found to screen the applied top gate bias, resulting in the on-state current increase without threshold voltage decrease under positive top gate bias. By investigating the effects of redundant electrodes and top gate, the electrical characteristics are characterized and verified. Furthermore, hot-carrier stress results in electron injection into the etch stop layer below the redundant drain electrode, and the distribution of trapped electrons is confined in the region below the redundant drain electrode. This trapping characteristic brings about a two-stage rise in the gate-to-source capacitance curve. The relationship between the length of redundant drain electrode and the height of first stage in gate-to-source capacitance curve reveals that the two-stage rise behavior is strongly affected by the drain electrode. Modulation of energy band during C-V measurement with top gate bias is employed to verify the degradation behavior after hot-carrier stress, and the corresponding response of gate-to-source and gate-to-drain capacitances verify the proposed model.
Impacts of light illumination on hot-carrier effect in InGaZnO thin-film transistors are also investigated, with results indicating that the hole-trapping effect, rather than the common trap-state generation induced by hot-carrier effect, takes place near the drain side and is the dominant degradation mechanism. Although the degradation is not evident in I-V characteristics, C-V measurement indicates trap-assisted photo-generation holes are trapped at the interface or within the dielectric layer near the drain side. This hole-trapping phenomenon can be attributed to the opposing direction of transverse electric field near the source and drain sides. It can be deduced from the experimental results of stress Vg modulation and AC bias stress that the degradation behavior after gate/drain bias stress carried out under light illumination is dependent on the voltage across gate and source or drain. These strongly support hole-trapping occurring at the interface or within the dielectric near the drain side as the dominant mechanism responsible for the hump phenomenon in gate-to-drain capacitance curve.
目次 Table of Contents
摘要 iv
Abstract vi
Figure Captions xii

Chapter 1 Introduction 1
1.1 Overview of Active-Matrix Flat Panel Displays 1
1.2 Overview of Amorphous Oxide Semiconductors 2
1.3 Motivation 5

Chapter 2 - Parameter Extraction Methodology 12
2.1 The VT extraction method 12
2.2 The subthreshold swing extraction method 13
2.3 The carrier mobility extraction method 14

Chapter 3 - Investigations on Self-Heating Effect-Induced Degradation Behavior in a-InGaZnO Thin-Film Transistors
17
3.1 Introduction 17
3.2 Experiment 18
3.3 Results and Discussion 19
3.4 Summary 32

Chapter 4 - Characterization and Investigation of Hot-Carrier Effect in Via-Contact Type a-InGaZnO Thin-Film Transistors with an Etch Stop Layer 49
4.1 Introduction 49
4.2 Experiment 50
4.3 Results and Discussion 51
a. Effects of Top Gate Bias on Device Characteristics 51
b. Hot-Carrier Effect-Induced Degradation Behaviors 58
4.4 Summary 66

Chapter 5 - Investigating Degradation Behaviors Induced by Hot-Carriers under Light Illumination in InGaZnO Thin Film Transistors 82
5.1 Introduction 82
5.2 Experiment 83
5.3 Results and Discussion 84
5.4 Summary 91
Chapter 6 - Conclusion 104
參考文獻 References
Chapter 1 - Introduction
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Chapter 3 - Investigations on Self-Heating Effect-Induced Degradation Behavior in a-InGaZnO Thin-Film Transistors
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Chapter 4 - Characterization and Investigation of Hot-Carrier Effect in Via-Contact Type a-InGaZnO Thin-Film Transistors with an Etch Stop Layer
[1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, pp. 488-492, 2004.
[2] E. M. Fortunato, P. M. Barquinha, A. Pimentel, A. M. Gonçalves, A. J. Marques, L. M. Pereira, and R. F. Martins, “Fully Transparent ZnO Thin‐Film Transistor Produced at Room Temperature,” Advanced Materials, vol. 17, pp. 590-594, 2005.
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[8] T.-C. Chen, T.-C. Chang, T.-Y. Hsieh, W.-S. Lu, F.-Y. Jian, C.-T. Tsai, S.-Y. Huang, and C.-S. Lin, “Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor,” Applied Physics Letters, vol. 99, pp. 022104-022104-3, 2011.
[9] J.-H. Shin, J.-S. Lee, C.-S. Hwang, S.-H. K. Park, W.-S. Cheong, M. Ryu, C.-W. Byun, J.-I. Lee, and H. Y. Chu, “Light effects on the bias stability of transparent ZnO thin film transistors,” ETRI Journal, vol. 31, pp. 62-64, 2009.
[10] F. Libsch and J. Kanicki, “Bias‐stress‐induced stretched‐exponential time dependence of charge injection and trapping in amorphous thin‐film transistors,” Applied Physics Letters, vol. 62, pp. 1286-1288, 1993.
Chapter 5 - Investigating Degradation Behaviors Induced by DC and AC bias stress under Light Illumination in InGaZnO Thin Film Transistors
[1] P. Gorrn, M. Lehnhardt, T. Riedl, and W. Kowalsky, “The influence of visible light on transparent zinc tin oxide thin film transistors,” Applied Physics Letters, vol. 91, pp. 193504-193504-3, 2007.
[2] T.-C. Chen, T.-C. Chang, T.-Y. Hsieh, C.-T. Tsai, S.-C. Chen, C.-S. Lin, M.-C. Hung, C.-H. Tu, J.-J. Chang, and P.-L. Chen, “Light-induced instability of an InGaZnO thin film transistor with and without SiO passivation layer formed by plasma-enhanced-chemical-vapor-deposition,” Applied Physics Letters, vol. 97, p. 192103, 2010.
[3] P.-T. Liu, Y.-T. Chou, and L.-F. Teng, “Environment-dependent metastability of passivation-free indium zinc oxide thin film transistor after gate bias stress,” Applied Physics Letters, vol. 95, pp. 233504-233504-3, 2009.
[4] W.-F. Chung, T.-C. Chang, H.-W. Li, S.-C. Chen, Y.-C. Chen, T.-Y. Tseng, and Y.-H. Tai, “Environment-dependent thermal instability of sol-gel derived amorphous indium-gallium-zinc-oxide thin film transistors,” Applied Physics Letters, vol. 98, pp. 152109-152109-3, 2011.
[5] J.-H. Shin, J.-S. Lee, C.-S. Hwang, S.-H. K. Park, W.-S. Cheong, M. Ryu, C.-W. Byun, J.-I. Lee, and H. Y. Chu, “Light effects on the bias stability of transparent ZnO thin film transistors,” ETRI Journal, vol. 31, pp. 62-64, 2009.
[6] F. Libsch and J. Kanicki, “Bias‐stress‐induced stretched‐exponential time dependence of charge injection and trapping in amorphous thin‐film transistors,” Applied Physics Letters, vol. 62, pp. 1286-1288, 1993.
[7] K. Takechi, M. Nakata, T. Eguchi, H. Yamaguchi, and S. Kaneko, “Comparison of ultraviolet photo-field effects between hydrogenated amorphous silicon and amorphous InGaZnO4 thin-film transistors,” Japanese Journal of Applied Physics, vol. 48, p. 0203, 2009.
[8] T.-C. Chen, T.-C. Chang, C.-T. Tsai, T.-Y. Hsieh, S.-C. Chen, C.-S. Lin, M.-C. Hung, C.-H. Tu, J.-J. Chang, and P.-L. Chen, “Behaviors of InGaZnO thin film transistor under illuminated positive gate-bias stress,” Applied Physics Letters, vol. 97, pp. 112104-112104-3, 2010.
[9] T.-C. Chen, T.-C. Chang, T.-Y. Hsieh, W.-S. Lu, F.-Y. Jian, C.-T. Tsai, S.-Y. Huang, and C.-S. Lin, “Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor,” Applied Physics Letters, vol. 99, pp. 022104-022104-3, 2011.
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