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博碩士論文 etd-0616115-104146 詳細資訊
Title page for etd-0616115-104146
論文名稱
Title
兩級管線暨逐次逼近式類比數位轉換器之實現
Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
64
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2015-06-26
繳交日期
Date of Submission
2015-07-16
關鍵字
Keywords
逐次逼近式類比數位轉換器、動態比較器、非同步時序電路、外加最高位元比較器、錯誤校正電路、管線式類比數位轉換器
Successive Approximation ADC, Error correction, Dynamic comparator, Pipelined ADC, Additional comparator for MSB
統計
Statistics
本論文已被瀏覽 5712 次,被下載 96
The thesis/dissertation has been browsed 5712 times, has been downloaded 96 times.
中文摘要
本論文提出了一個兩級管線式暨連續逼近式類比數位轉換器,其中以兩級管線式架構減少高功率消耗的運算放大器之使用量,並且將傳統管線式類比數位轉換器中作為子類比數位轉換器的快閃式類比數位轉換器以逐次逼近式類比數位轉換器取代,同時將逐次逼近式類比數位轉換器前端之取樣保持電路以電容陣列取樣開關取代之,使得整個電路僅需要使用一個運算放大器電路,來達到低功率消耗之目標。
使用動態比較器以及非單調性電容陣列之切換方法,來降低整體的功率消耗。在子類比數位轉換器當中,採用改良式之電容陣列,使其相較於傳統二進制電容陣列有更低的功率消耗。在電路取樣階段時,使用額外之比較器電路用來進行最高位元之轉換,提高類比數位轉換器之換速度,同時亦可減輕運算放大器的設計難度。另外,在第二級電路使用錯誤校正電路來加強轉換之精準度。
Abstract
A high speed and low power Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter is proposed in this thesis. Using only two stage in the proposed ADC architecture, and reduce the requirement of power hungry operation amplifier. The pipelined stage replace the Flash ADC by SAR ADC. Removing the front-end sample-and-hold circuit by capacitor array in the SAR ADCs and sample switch. Hence, the whole circuit only requires one operation amplifier.
Using dynamic comparators which consume no static power consumption. Capacitor arrays used in the SAR ADC adopt the monotonic switching procedure to achieve energy efficient and high speed applications. An additional comparator for MSB is designed for the ADC using in sample phase. The error correction Logic is employed for higher resolution.
目次 Table of Contents
論文審定書 ii
摘要 iii
ABSTRACT iv
目錄 v
圖目錄 viii
表目錄 x
第1章 緒論 1
1.1 研究動機 1
1.2 論文組織架構 2
第2章 類比數位轉換器架構介紹 3
2.1 類比數位轉換器的相關性能參數 3
2.1.1 靜態性能參數 3
2.1.1.1 微分非線性度誤差(Differential Nonlinearity, DNL) 3
2.1.1.2 整體非線性度誤差(Integral Non-Linearity, INL) 4
2.1.1.3 遺失碼(Missing Code) 5
2.1.1.4 偏移誤差與增益誤差(Offset and Gain Error) 5
2.1.2 動態性能參數 6
2.1.2.1 訊號雜訊比(Signal-to-Noise Ratio, SNR) 6
2.1.2.2 訊號雜訊失真比(Signal-to-Noise & Distortion Ratio, SNDR) 7
2.1.2.3 無寄生動態範圍(Spurious Free Dynamic Range, SFDR) 7
2.2 常見的類比數位轉換器架構[1][3] 7
2.2.1 快閃式類比數位轉換器(Flash ADC) 7
2.2.2 兩階段類比數位轉換器(Two-step ADC) 9
2.2.3 管線式類比數位轉換器(Pipeline ADC) 9
2.2.4 逐次逼近式類比數位轉換器(Successive Approximation ADC) 11
第3章 類比數位轉換器之系統特性分析 13
3.1 取樣保持電路(Sample and hold circuit, S/H) 13
3.2 電容陣列(Capacitor Array) 14
3.2.1 二進制權重電容陣列(Binary Weighted Capacitor Array) 14
3.2.2 C-2C電容陣列(C-2C Capacitor Array) 15
3.2.3 單調性電容開關之二進制權重電容陣列(Binary Weighted Array with Monotonic Capacitor Switching, BWMC) 16
3.3 比較器電路(Comparator) 17
3.3.1 靜態閂鎖比較器(Static Latched Comparator) 17
3.3.2 Class-AB閂鎖比較器(Class-AB Latched Comparator) 18
3.3.3 動態閂鎖比較器(Dynamic Latched Comparator) 19
第4章 類比數位轉換器系統實現 21
4.1 簡介 21
4.2 比較器電路(Comparator) 23
4.3 外加最高位元比較器 25
4.4 逐次逼近暫存器邏輯電路(Successive Approximation Register logic, SAR logic) 26
4.5 錯誤校正電路(Error Correction Logic) 29
4.6 第一級子類比數位轉換器電路 31
4.6.1 應用於第一級管線暨逐次逼近式架構之電容陣列 34
4.6.2 數位類比轉換器邏輯電路 39
4.7 第二級子類比數位轉換器電路 41
4.7.1 應用於第二級管線暨逐次逼近式架構之電容陣列 44
4.7.2 數位類比轉換器邏輯電路 47
第5章 結論 52
5.1 結論 52
5.2 未來改進方向 52
參考文獻 53
參考文獻 References
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