本論文提出了一個高調頻範圍，低相位雜訊與快速鎖定全積體化除整數之頻率合成器。此頻率合成器主要應用於IEEE 802.11ac Wi-Fi，提供4.2GHz至5.7GHz的本地振盪器，並應用於射頻收發機的前端電路。本論文所提出的頻率合成器包含頻率偵測器(Phase / Frequency Detector, PFD)及電荷幫浦(Charge Pump, CP)、低通迴路濾波器(Low Loop filter, LPF)、壓控振盪器(Voltage control Oscillator, VCO)、可程式化轉導放大器(Programmable Operational Transconductance Amplifier, P-OTA) 、電壓比較器(Comparator) 、鎖定偵測器(Lock Detector)、控制邏輯閘(Control Logic)、上下計數器(Up/Down Counter)以及雙模計數器(Pluse-Swallow Counter)。
在此系統中使用P-OTA，在V_tune與LPF之間藉由回授電壓進而提升gm值，將加大流入LPF之電流，以達到快速鎖定之目的。
所提出的電路架構使用TSMC 90nm 1P9M CMOS製程實現，經模擬結果顯示功率消耗為11.37mW，鎖定時間為5.1μs，輸出頻率為4.046GHz~5.742GHz，晶片面積為684um × 531um。

This thesis presents a wide tuning, low phase noise, and fast locking CMOS integer-N frequency synthesizer with 1 V power supply. It can be used for IEEE 802.11ac unlicensed band of Wi-Fi (Wireless Fidelity). It provides one ration frequency ranged from 4.046GHz to 5.742GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a Phase / Frequency Detector, a Charge Pump, a voltage control oscillator, Programmable Operational Transconductance amplifier (P-OTA), Comparator, Control Logic, Up/Down Counter, and a pulse-swallow divider. Using the P-OTA in PLL system, by V_tuneand LPF feedback voltage to increase the gm value that increase in the LPF current to speed up the lock time.
The proposed PLL is implemented in TSMC 90nm 1P9M RF technology. The simulation results show that the power dissipation is 11.37mW, the output frequency is 4.046GHz~5.742GHz, the lock time is 5.1μs , and the chip size is 684um × 531um.

第1章 緒論 1
1.1 研究動機 1
1.2 論文組織架構 1
第2章 鎖相迴路基本觀念 2
2.1 鎖相迴路基礎觀念 2
2.2 鎖相迴路各項架構及操作理 3
2.2-1 相位頻率偵測器（Phase Frequency Detector, PFD） 3
2.2-2 電荷幫浦(Charge Pump, CP) 5
2.2-3 迴路濾波器(Loop Filter, LPF) 6
2.2-4 電壓控制振盪器(Voltage Control Oscillator, VCO) 7
2.2-5 除頻器(Divider) 9
2.3 加速鎖定類型鎖相迴路介紹 10
2.3-1 使用連續時間相位頻率偵測器快速鎖定技術於鎖相迴路 10
2.3-2 使用雙斜率相位頻率偵測器與充電泵快速鎖定鎖相迴路 12
2.3-3 結論 13
第3章 鎖相迴路之系統特性分析及實現 14
3.1 架構簡介 14
3.2 相位頻率偵測器(Phase Frequency Detector, PFD) 17
3.3 電荷幫浦(Charge pump, CP) 20
3.4 可程式化轉導放大器 Programmable OTA 23
3.5 迴路濾波器與轉導放大器(Low Pass Filter, LPF and，OTA) 25
3.6 壓控震盪器VCO 29
3.7 比較器 Comparator 31
3.8 除頻器(Divider) 33
3.9 上/下計數器UP/DN Counter 36
3.10 鎖定偵測器Lock Detector 38
3.11 電壓比較邏輯(Voltage Comparator Logic) 39
3.12 電壓選擇器(Voltage Selection) 40
3.13 控制邏輯(Control Logic) 41
3.14 暫存器(Register) 41
第4章 使用可程式化轉導放大器於鎖相迴路之電路模擬 42
4.1 簡介 42
4.2 鎖相迴路之各項Block模擬 42
4.2-1 頻率相位偵測器模擬 42
4.2-2 電荷幫浦模擬 44
4.2-3 壓控震盪器模擬 44
4.2-4 可程式化轉導放大器模擬 46
4.3 鎖相迴路系統模擬 47
第5章 鎖相迴路電路佈局與模擬 48
5.1 鎖相迴路電路佈局圖 48
5.2 效能比較 50
第6章 結論 51
6.1 結論 51
6.2 未來改進方向 51

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