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博碩士論文 etd-0617114-152230 詳細資訊
Title page for etd-0617114-152230
論文名稱
Title
運用圖形處理器之光通訊數位同調接收器之研究
Investigation of GPU-based Real Time Digital Coherent Receiver for Optical Transmission System
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
53
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2014-07-15
繳交日期
Date of Submission
2014-07-18
關鍵字
Keywords
相位偵測、非同步執行、平行處理、數位訊號處理、同調偵測、統一計算架構、圖形處理器
Digital Signal Processing, Phase estimation, Asynchronous execution, Parallel processing, CUDA, Coherent detection, Graphic Processing Unit
統計
Statistics
本論文已被瀏覽 5668 次,被下載 104
The thesis/dissertation has been browsed 5668 times, has been downloaded 104 times.
中文摘要
同調光通訊系統已經受到世界各方的注意,若將此技術應用在光纖通訊上,可以更有效的利用光載波並進一步實現高頻譜效率的通訊系統。在1980年代,為了實現零差檢測(Homodyne Detection),使用光鎖相迴路(Optical Phase Locked Loop)是必須的,然而時至今日此種迴路仍難以實現。

近年來,人們傾向使用數位訊號處理(DSP)來取代光鎖相迴路以實現零差檢測。由於高速通訊系統的資料量龐大,所以實時(Real Time)操作的數位訊號處理仍然是一個難題,因此,我們嘗試利用搭載高效能圖形處理器(GPU)的個人電腦來進行資料的平行處理(Parallel Processing)。至今我們已完成了CUDA程式的演算法,然而在實時的情況下,CPU與GPU之間的資料傳輸速度會受到傳輸介面的影響,這篇碩士論文目的在解決這個瓶頸。
Abstract
The coherent optical communication system has been paid much attention in the world. With this technique applied to optical communication, we can make more efficient use of the light carrier. Furthermore, we can realize a high efficiency communication system. In 1980s, in order to realize homodyne detection, optical phase locked loop (OPLL) is needed. Unfortunately, it is still difficult to realize even nowadays.
Recently, people tend to use digital signal processing in place of OPLL to realize homodyne detection coherent receiver. The implementation of real-time digital signal processing (DSP) is still an issue due to the large amount of high-speed communication data. Therefore, we try to utilize a personal computer which equipped with high-performance Graphic Processing Unit (GPU) card for parallel signal processing. We had completed the algorithm of program by CUDA technology, but for the real-time operation, the speed of data transfer between the CPU and the GPU device was an issue. It was affected by the interface. This master thesis tries to solve this bottleneck.
目次 Table of Contents
致謝 i
中文摘要 ii
Abstract iii
Contents iv
圖目錄 vi
表目錄 viii
Chapter 1 Introduction 1
1.1 Optical coherent system 1
1.2 Motivation of this thesis 4
1.3 Previous achievement 5
1.4 Structure of this Thesis 8
Chapter 2 GPU Calculation Technology 9
2.1 Introduction 9
2.2 CUDA parallel computing architecture 11
2.3 Processing flow 16
2.4 Algorithm 17
2.4.1 Phase compensation 18
2.4.2 Differential decoding 21
2.4.3 BER measurement 23
2.5 Summary 24
Chapter 3 Time Reduction of Data Transfer 25
3.1 Introduction 25
3.2 Direct Memory Access 29
3.3 Result 30
Chapter 4 Asynchronous Concurrent Execution 33
4.1 CUDA stream 33
4.2 Analysis tool and result 36
4.3 Preparation for real-time operation 37
4.4 Conclusion 39
Chapter 5 Summary 40
References 41
Acronyms 43
參考文獻 References
[1] Dany-Sebastien Ly-Gagnon, Tsukamato, Kazuhiro Katoh, and Kazuro Kikuchi, “ Coherent detection of optical quadrature phase-shift keying signals with carrier phase estimation ”, journal of lightwave technology,Vol. 24, NO. 1, page 12-21, Jan. 2006
[2] Jens C. Rasmussen, Takeshi Hoshida, Hisao Nakashima, “Digital Coherent Receiver Technology for 100-Gb/s Optical Transport Systems”, FUJITSU Sci. Tech. J., Vol. 46, No. 1, pp. 63-71, January 2010
[3] Govind P. Agrawal,"Fiber-Optic Communication Systems", Edition: 3, Chapter 10, June 15, 2002, John Wiley & Sons, Inc.
[4] Reinhold Noe, “Phase noise tolerant synchronous QPSK receiver concept with digital I&Q”, Univ. Paderborn, EIM-E, Warburger Str. 100, D-33098 Paderborn, Germany.
[5] J. Sanders and E. Kandrot, CUDA by example: an introduction to general-purpose GPU programming, 1th ed. United States of America, 2011.
[6] Cheng-Chieh Chang,”GPU-based real time digital coherent receiver for optical transmission system”, Department of Photonics, National Sun Yat-sen University, July 2013
[7] Akshay Shukla,”Simulation on programmable graphics hardware (GPUs)”, 04/08/2010, http://run.usc.edu/cs599-s10/scribeNotes/Akshay_Shukla_scribe_notes.pdf
[8] Yukai Hung,"CUDA Asynchronous Memory Usage and Execution", Department of Mathematics National Taiwan University
[9] NVidia Company, "NVIDIA CUDA C Programming Guide", Edition 4.2, April 2012
[10] NVidia Company, "CUDA C BEST PRACTICES GUIDE", Edition 4.1, January 2012
[11] NVidia Company, "Whitepaper: NVIDIA’s Next Generation CUDA Compute Architecture: Fermi", Edition 1.1,2009
[12] NVidia Company, "Whitepaper: NVIDIA’s Next Generation CUDA Compute Architecture: Kepler TM GK110", Edition 1.0,2012
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