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博碩士論文 etd-0617115-162202 詳細資訊
Title page for etd-0617115-162202
論文名稱
Title
高性能低溫多晶矽薄膜電晶體之研究
Study of High Performance Low-Temperature Poly-Si Thin-Film Transistors
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
74
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2015-07-07
繳交日期
Date of Submission
2015-07-20
關鍵字
Keywords
短通道效應、金屬誘發側向結晶法、固相結晶法、多晶矽薄膜電晶體、高介電常數材料當介電層
Metal-induced lateral crystallization (MILC), High-k Gate Dielectric, short channel effect (SCE), Solid Phase Crystallization (SPC), low-temperature poly-Si thin film transistors (LTPS-TFTs)
統計
Statistics
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The thesis/dissertation has been browsed 5684 times, has been downloaded 390 times.
中文摘要
多晶矽薄膜電晶體因為具有較高的載子遷移率,所以被認為可以廣泛的應用
在主動矩陣式液晶顯示器的開關元件上。而為了提升元件的特性,元件的尺寸不
斷的微縮下去,勢必會發生一些非理想效應,此時就有人提出些許方法可以在維
持元件尺寸大小情況下,提升元件的電特性。
多晶矽薄膜電晶體為了提升元件特性,可以對氧化層厚度做適當的微縮,但
是當微縮到一定厚度時,會因為氧化層厚度太薄的關係,而產生不可預期的閘極
漏電流,且氧化層厚度太薄也有可靠度的問題存在;另外,過多的晶粒界面及缺陷
存在於通道中將大幅地劣化多晶矽薄膜電晶體的特性。
金屬誘發側向結晶法減少了晶粒邊界以及存在於通道中的缺陷,而高介電常
數材料當介電層會大幅提升閘極電容值,進而提升元件特性。
本篇論文中,使用了金屬誘發側向結晶法的方式並且搭配高介電常數材料當
介電層,大幅的提升元件的特性,與傳統的固相結晶法搭配二氧化矽當介電層相
比,有著非常好的電特性,包括了載子遷移率和次臨界擺福。另外,其對於短通
道效應量測和變溫量測之電性變化,也將進行探討。
Abstract
High performance low-temperature poly-Si thin film transistors (LTPS-TFTs) have
been intensively investigated for the application of the active matrix liquid-phase crystal
displays. In this article, high performance LTPS-TFTs are fabricated by using HfO2 gate
dielectric and with Metal-induced lateral crystallization (MILC) channel layer.
MILC LTPS-TFT with High-k Gate Dielectric, high field-effect mobility , ultralow
subthreshold swing are achieved without any defect passivation methods. These
significant improvements are due to the MILC channel film and the very high
gate-capacitance density provided by HfO2 gate dielectric.
In Solid Phase Crystallization (SPC)-TFT’s, the grain boundaries are randomly
oriented. It is also observed in this work that while the MILC-TFT with High-k Gate
Dielectric are less sensitive to short channel effect (SCE).
目次 Table of Contents
目錄
論文審定書 ............................................................................................................... i
論文公開授權書 ...................................................................................................... ii
致謝 ......................................................................................................................... iii
摘要 ......................................................................................................................... iv
Abstract ..................................................................................................................... v
表目錄 ................................................................................................................... viii
圖目錄 ..................................................................................................................... ix
第一章 緒論 ...................................................................................................... 1
1-1 薄膜電晶體基本架構 ................................................................................................ 1
1-1-1 薄膜電晶體基本運作原理 .................................................................................... 1
1-2 多晶矽與非晶矽 ........................................................................................................ 2
1-2-1 單晶MOSFET 與多晶矽薄膜電晶體 ................................................................... 2
1-3 再結晶法製程技術 .................................................................................................... 3
1-3-1 準分子雷射結晶法(ELC, Excimer Laser Crystallization) .................................... 4
1-3-2 固相結晶法(SPC, Solid Phase Crystallization) ..................................................... 4
1-4 金屬誘發側向結晶法(MILC, MetalInduced Lateral Crystallization) ..................... 5
1-4-1 金屬誘發側向結晶法(MILC)介紹 ........................................................................ 5
1-4-2 MILC/MIC 之介面影響 ......................................................................................... 7
1-5 短通道效應(SCE, Short-Channel Effect) ............................................................... 8
1-5-1 短通道效應對結晶法之影響 ................................................................................ 9
1-6 高介電常數材料之介電層(High- κ Gate Dielectric) ............................................. 10
第二章 實驗流程與元件製作 ........................................................................ 19
2-1 NTFT 使用固相結晶法 ........................................................................................... 19
2-2 NTFT 使用金屬誘發側向結晶法 ........................................................................... 20
2-2 重要電性參數之萃取 .............................................................................................. 21
2-2-1 臨界電壓 .............................................................................................................. 21
2-2-2 次臨界擺幅 .......................................................................................................... 21
2-2-3 轉移電導(gm) ........................................................................................................ 22
2-2-4 載子遷移率 ......................................................................................................... 22
2-2-5 電流開關比(on/off Ratio) ................................................................................... 23
2-3 實驗動機與目的 ..................................................................................................... 23
第三章 結果與討論 ........................................................................................ 32
3-1 MILC&High- κ與SPC&SiO2 之電性比較 ............................................................ 32
3-1-1 MILC&High-κ 與SPC&SiO2 之輸出特性曲線(ID-VD) ..................................... 34
3-2 MILC&High- κ與SPC&SiO2之通道長度調變 ..................................................... 34
3-3 MILC&High-κ 之元件比較 .................................................................................... 36
3-4 溫度效應 .................................................................................................................. 37
第四章 結論 .................................................................................................... 39
參考文獻 ................................................................................................................ 59
表目錄
表3-1 NTFT VD=0.1 時之各項電性參數 ..................................................................... 40
表3-2 PTFT VD=0.1 時之各項電性參數 ..................................................................... 40
表3-3 MILC&High-κ 元件VD=0.1 時之各項電性參數 ............................................. 41
表3-4 SPC&SiO2元件VD=0.1 時之各項電性參數 .................................................... 41
圖目錄
圖1-1 薄膜電晶體基本架構 ......................................................................................... 12
圖1-2 PTFT 通道累積電洞 .......................................................................................... 12
圖1-3 NTFT 通道累積電子 ......................................................................................... 12
圖1-4 非晶、多晶及單晶等三種晶體的一般形式 ..................................................... 13
圖1-5 固相結晶法(左)與準分子雷射結晶法(右)之表面圖........................................ 13
圖1-6 金屬誘發側向結晶法之長晶示意圖 ................................................................. 13
圖1-7 金屬誘發側向結晶之晶粒示意圖 ................................................................... 14
圖1-8 Ni-Si 反應活化能圖 ......................................................................................... 14
圖1-9 c-Si 在NiSi2/a-Si 介面形成的結晶成長機制 ................................................. 15
圖1-10 Si 與NiSi2晶體結構 ........................................................................................ 15
圖1-11 自我對準下的金屬誘發側向結晶 ................................................................... 15
圖1-12 overlapping MMGBs 以及通道接面能障示意圖 ........................................... 16
圖1-13 漏電流之機制 ................................................................................................. 16
圖1-14 MMGBs offset 之製程示意圖 .......................................................................... 16
圖1-15 MMGB offset 以及通道接面能障示意圖 ....................................................... 17
圖1-16 長通道下能障圖 ............................................................................................... 17
圖1-17 短通道下之能障圖 ........................................................................................... 17
圖1-18 汲極端影響能障示意圖 ................................................................................... 18
圖1-19 固相結晶法與金屬誘發側向結晶法之能障與晶粒邊界分布圖 ................... 18
圖1-20 High-κ Gate Dielectric 多晶矽薄膜電晶體示意圖 ......................................... 18
圖2-1 步驟一 ................................................................................................................. 25
圖2-2 步驟二 ................................................................................................................. 25
圖2-3 步驟三 ................................................................................................................. 25
圖2-4 步驟四 ................................................................................................................. 25
圖2-5 步驟五 ................................................................................................................. 26
圖2-6 步驟六 ................................................................................................................. 26
圖2-7 步驟七 ................................................................................................................. 26
圖2-8 步驟八 ................................................................................................................. 27
圖2-9 步驟九 ................................................................................................................. 27
圖2-10 步驟十 ............................................................................................................... 28
圖2-11 步驟十一 ........................................................................................................... 28
圖2-12 步驟十二 ........................................................................................................... 29
圖2-13 本實驗固相結晶法之結構圖 ........................................................................... 29
圖2-14 步驟四之一 ....................................................................................................... 30
圖2-15 步驟四之二 ....................................................................................................... 30
圖2-16 步驟四之三 ....................................................................................................... 30
圖2-17 步驟四之四 ....................................................................................................... 30
圖2-18 步驟七之一 ....................................................................................................... 31
圖2-19 本實驗金屬誘發側向結晶法之結構圖 ........................................................... 31
圖3-1 .............................................................................................................................. 42
圖3-2 NTFT 在VD=0.1 之轉移特性曲線(ID-VG和gm) .............................................. 42
圖3-3 NTFT 在VD=1 之轉移特性曲線(ID-VG和gm) ................................................. 43
圖3-4 PTFT 在VD=0.1 之轉移特性曲線(ID-VG和gm) ............................................... 43
圖3-5 PTFT 在VD=1之轉移特性曲線(ID-VG和gm) .................................................. 44
圖3-6 MILC&High-κ 與SPC&SiO2之NTFT 輸出特性曲線 .................................... 44
圖3-7 MILC&High- κ 與SPC&SiO2之PTFT 輸出特性曲線 .................................... 45
圖3-8 MILC&High- κ NTFF VD=0.1 通道長度調變轉移特性曲線 ........................... 45
圖3-9 MILC&High- κ NTFF VD=1通道長度調變轉移特性曲線 .............................. 46
圖3-10 SPC&SiO2 NTFF VD=0.1 通道調變轉移特性曲線 ......................................... 46
圖3-11 SPC&SiO2 NTFF VD=1通道調變轉移特性曲線 ............................................ 47
圖3-12 NTFT 通道長度調變下的臨界電壓 ................................................................ 47
圖3-13 NTFT 通道長度調變下的次臨界擺幅 ............................................................ 48
圖3-14 MILC&High- κ PTFF VD=0.1 通道長度調變轉移特性曲線 .......................... 48
圖3-15 MILC&High- κ PTFF VD=1通道長度調變轉移特性曲線 ............................ 49
圖3-16 SPC&SiO2 PTFF VD=0.1 通道調變轉移特性曲線 ......................................... 49
圖3-17 SPC&SiO2 PTFF VD=1通道調變轉移特性曲線 ............................................ 50
圖3-18 PTFT 通道長度調變下的臨界電壓 ................................................................ 50
圖3-19 PTFT 通道長度調變下的次臨界擺幅 ............................................................ 51
圖3-20 MILC&High-κ 之各元件轉移特性曲線 ......................................................... 51
圖3-21 SPC&SiO2之各元件轉移特性曲線 ................................................................ 52
圖3-22 MILC&High-κ NTFF VD=0.1 變溫量測轉移特性曲線 ................................. 52
圖3-23 MILC&High- κ NTFF VD=1變溫量測轉移特性曲線 .................................... 53
圖3-24 SPC&SiO2 NTFF VD=0.1 變溫量測轉移特性曲線 ......................................... 53
圖3-25 SPC&SiO2 NTFF VD=1變溫量測轉移特性曲線 ............................................ 54
圖3-26 NTFT 變溫量測下的次臨界擺幅 .................................................................... 54
圖3-27 NTFT 變溫量測下的漏電流 ............................................................................ 55
圖3-28 MILC&High- κ PTFF VD=0.1 變溫量測轉移特性曲線 .................................. 55
圖3-29 MILC&High- κ PTFF VD=1變溫量測轉移特性曲線 ..................................... 56
圖3-30 SPC&SiO2 PTFF VD=0.1 變溫量測轉移特性曲線 ......................................... 56
圖3-31 SPC&SiO2 PTFF VD=1變溫量測轉移特性曲線 ............................................ 57
圖3-32 PTFT 變溫量測下的次臨界擺幅 .................................................................... 57
圖3-33 PTFT 變溫量測下的漏電流 ............................................................................ 58
參考文獻 References
參考文獻
[1] D. A. Neamen, Semiconductor physics and devices: basic principles:
McGraw-Hill, 2011.
[2] I. W. Wu, H. Tiao-Yuan, W. B. Jackson, A. G. Lewis, and A. Chiang,
"Passivation kinetics of two types of defects in polysilicon TFT by plasma
hydrogenation," IEEE Electron Device Letters, vol. 12, pp. 181-183, 1991.
[3] W. C. Y. Ma, C. Tsung-Yu, Y. Chi-Ruei, C. Tien-Sheng, T. Lei, x, et al.,
"Channel film thickness effect of low-temperature polycrystalline-silicon
thin-film transistors," IEEE Transactions on Electron Devices, vol. 58, pp.
1268-1272, 2011.
[4] W. Man, Z. Jin, G. A. Bhat, P. C. Wong, and K. Hoi Sing, "Characterization of
the MIC/MILC interface and its effects on the performance of MILC thin-film
transistors," IEEE Transactions on Electron Devices, vol. 47, pp. 1061-1067,
2000.
[5] G. K. Giust and T. W. Sigmon, "High-performance thin-film transistors
fabricated using excimer laser processing and grain engineering," IEEE
Transactions on Electron Devices, vol. 45, pp. 925-932, 1998.
[6] C.-L. Fan and M.-C. Chen, "Correlation between electrical characteristics and
oxide/polysilicon interface morphology for excimer-laser-annealed poly-Si
TFTs," Journal of The Electrochemical Society, vol. 149, pp. G567-G573,
October 1, 2002 2002.
[7] E. Ibok and S. Garg, "A characterization of the effect of deposition temperature
on polysilicon properties: morphology, dopability, etchability, and polycide
properties," Journal of The Electrochemical Society, vol. 140, pp. 2927-2937,
October 1, 1993 1993.
[8] M. S. Haque, H. A. Naseem, and W. D. Brown, "Aluminum ‐ induced
crystallization and counter ‐ doping of phosphorous ‐ doped hydrogenated
amorphous silicon at low temperatures," Journal of Applied Physics, vol. 79, pp.
7529-7536, 1996.
[9] O. Nast, S. Brehme, D. H. Neuhaus, and S. R. Wenham, "Polycrystalline silicon
thin films on glass by aluminum-induced crystallization," IEEE Transactions on
Electron Devices, vol. 46, pp. 2062-2068, 1999.
[10] M. Zhiguo, W. Mingxiang, and W. Man, "High performance low temperature
metal-induced unilaterally crystallized polycrystalline silicon thin film
transistors for system-on-panel applications," IEEE Transactions on Electron
60
Devices, vol. 47, pp. 404-409, 2000.
[11] S.-W. Lee and S.-K. Joo, "Low temperature poly-Si thin-film transistor
fabrication by metal-induced lateral crystallization," IEEE Electron Device
Letters, vol. 17, pp. 160-162, 1996.
[12] C. Hayzelden and J. L. Batstone, "Silicide formation and silicide‐mediated
crystallization of nickel‐implanted amorphous silicon thin films," Journal of
Applied Physics, vol. 73, pp. 8279-8289, 1993.
[13] K. R. Olasupo and M. K. Hatalis, "Leakage current mechanism in sub-micron
polysilicon thin-film transistors," IEEE Transactions on Electron Devices, vol.
43, pp. 1218-1223, 1996.
[14] K. Gi-Bum, Y. Yeo-Geon, M.-S. Kim, J. Hunjoon, S.-W. Lee, and S.-K. Joo,
"Electrical characteristics of MILC poly-Si TFTs with long Ni-offset structure,"
IEEE Transactions on Electron Devices, vol. 50, pp. 2344-2347, 2003.
[15] W. C. Y. Ma, C. Tsung-Yu, L. Je-Wei, and C. Tien-Sheng, "Oxide thinning and
structure scaling down effect of low-temperature poly-Si thin-film transistors,"
Journal of Display Technology, vol. 8, pp. 12-17, 2012.
[16] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices: Cambridge
University Press, 2009.
[17] G. A. Bhat, Z. Jin, H. S. Kwok, and W. Man, "Effects of longitudinal grain
boundaries on the performance of MILC-TFTs," IEEE Electron Device Letters,
vol. 20, pp. 97-99, 1999.
[18] Y. Ming-Jui, C.-H. Chien, L. Yi-Hsien, S. Chih-Yen, and H. Tiao-Yuan,
"Electrical properties of low-temperature-compatible p-channel
polycrystalline-silicon TFTs using high-κ gate dielectrics," IEEE Transactions
on Electron Devices, vol. 55, pp. 1027-1034, 2008.
[19] P. Tung-Ming, C. Ching-Lin, and W. Tin-Wei, "High-performance poly-silicon
TFTs using a high-κ PrTiO3 gate dielectric," IEEE Electron Device Letters, vol.
30, pp. 39-41, 2009.
[20] B. F. Hung, K. C. Chiang, C. C. Huang, A. Chin, and S. P. McAlister,
"High-performance poly-silicon TFTs incorporating LaAlO3 as the gate
dielectric," IEEE Electron Device Letters, vol. 26, pp. 384-386, 2005.
[21] P. Tung-Ming, C. Ching-Lin, and W. Tin-Wei, "High-performance poly-silicon
TFTs using HfO2 gate dielectric," IEEE Electron Device Letters, vol. 30, pp.
39-41, 2009.
[22] M. Ming-Wen, C. Tsung-Yu, W. Woei-Cherng, C. Tien-Sheng, T. Lei, x, et al.,
"Characteristics of HfO2/poly-Si interfacial layer on CMOS LTPS-TFTs with
HfO2 gate dielectric and O2 plasma surface treatment," IEEE Transactions on
Electron Devices, vol. 55, pp. 3489-3493, 2008.
[23] C. F. Cheng, T. C. Leung, M. C. Poon, and M. Chan, "Large-grain polysilicon
crystallization enhancement using pulsed RTA," IEEE Electron Device Letters,
vol. 25, pp. 553-555, 2004.
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