多核心處理器已成為目前處理器架構主流，單晶片多核心透過提升指令層級並行度與執行緒層級並行度來增進系統效能，因此，在此架構下核心間資料傳輸效率將決定多核心系統之效能，本論文將分為多核心晶片網路中，以公平仲裁機制改善節點飢餓與熱點問題，另一部分提出緩衝器機制用來增進晶片網路節點資料抓取機制，以改善傳統記憶體層級與處理器間速度差異造成之效能損失。
多核心晶片網路中，用來仲裁核心間溝通遭遇碰撞策略之公平性、可延展性與仲裁策略之簡化皆重要地影響著多核心系統之效能，不公平的策略將導致飢餓與熱點的問題,特別在高負載的晶片網路下,此外仲裁策略的硬體複雜度亦必須被考量，針對這些課題,本論文提出一可適當調整網路節點優先權之簡單且公平仲裁策略，在傳輸的初始狀態，每節點有各自獨立的優先權，當節點間的競爭發生時,競爭失敗者將與勝利者交換其優先權權重做為下次連線的依據，這原則可保證勝利者在下一次連線的機會將被降低，否則該勝利者增加其優先權，本論文提出之機制僅需藉由簡單的比較與交換的運作，即可有效率地達到整體系統競爭之公平性，此外，考量速度與時脈偏移，本論文將以非同步電路完成，模擬結果呈現藉由這公平的策略，本論文提出的排程減緩飢餓的問題、保證免除死結和改進熱點問題,在多節點的系統中，該方法能對於全系統有效率地提供公平的仲裁。
傳統記憶體層級架構雖然可以順暢指令與資料流，然而，指令流與資料流的頻寬不足仍然是提升整體系統效能的主要挑戰。為了增進指令與資料的抓取，在此提出一利用時間與空間的局部性特質切換緩衝器之存取的緩衝機制，當指令或資料存於緩衝器，該指令或資料將可被重新使用，此時，用來預先抓取資料之預先抓取緩衝器將位預先抓取於該緩衝器中。模擬及實作結果顯示，此機制在緩衝器擴充深度為3與每單位緩衝器大小為64Kbyte，指額外增加4%的硬體成本為最有效率之使用，該提出之緩衝器機制之命中率能優於loop buffer 22% 的指令抓取與7% 先進先出策略的資料抓取。

Multi-core systems in single chip exploit ILP (Instruction-Level Parallelism) and TLP (Thread-Level Parallelism) to improve the system performance. Therefore, efficiency of transferring data among cores dominates the multi-core system performance. This work proposed a fair arbitration strategy to improve starvation and hotspot problems for multi-core systems in on-chip networks. On the other hands, to reduce the gap between the traditional memory hierarchy and processors, a novel buffering mechanism is proposed to improve the data fetch for network-on-chip nodes.
On multi-core systems in on-chip networks, the global fairness, scalability, and simplicity of the strategy used to arbitrate the communications of collisions among cores have substantial effects. An unfair strategy causes starvation and hotspot problems, especially under heavy loads. In addition, the complexity of the hardware of the arbitration strategy that is involved in the on-chip environment must also be considered. To address these issues, this paper presents a simple and fair strategy that involves properly adjusting priorities of nodes. In the initial states of transferring data, each node has unique priorities. When competition among nodes occurs at a particular network, the loser swaps their priority with the priority of the winner. This principle guarantees that the opportunities of winners to decrease for the subsequent connection, whereas the priorities of winners increase. Using simple comparing and exchanging operations, the proposed arbitration strategy is an efficient global fairness strategy. Moreover, considering the speed and clock skew, asynchronous circuits are used for implementations. Simulation results demonstrate that by applying a fair strategy, the proposed scheme alleviates starvation, guarantees deadlock freedom, and improves hotspot problems. In a large system, this approach efficiently provides experience of service.
The traditional memory hierarchy design can smooth the data stream and instruction stream. However, the bandwidth of the instruction stream and data stream are still the main challenge for high-performance microprocessor systems. To improve the data and instruction fetchers, the proposed buffering architecture can exploits both the temporal and spatial localities with a relation-exchanging buffering mechanism. On buffers hit, the instruction or data can be reused. At the same time, the prefetching mechanism will be enabled to prefetch the instruction/data being used in the near future. According to the simulation results, the proposed buffering mechanism with the depth 3 and 64-byte line size, which only needs extra 4% hardware cost, is a cost-effectiveness choice. The hit rate of the proposed buffer mechanism can 22% outperforms that of loop buffer architecture to fetch instruction stream and 7% outperform that of First-In-First-Out (FIFO) strategy to fetch data stream.

論文審定書 i
誌　謝 iii
摘　要 iv
Abstract vi
Table of Contents viii
List of Figures x
List of Tables xiv
Chapter 1 Introduction 1
1.1 Fairness of arbitration strategies 3
1.2 Buffering mechanisms for data fetch 6
1.3 Centralized and Distributed Strategy approaches 7
Chapter 2 Background and Relevant Works 9
2.1 Multi-core Communications Overview 9
2.2 Background 12
2.3 Arbitration Strategies 14
2.4 Buffering mechanism 16
2.4.1 General Mechanisms 17
2.4.2 Instruction Stream for VLIW Architectures 20
Chapter 3 Buffering Mechanism for instruction and data streams 25
3.1 ABP buffer 27
3.1.1 Design of the ABP buffer 27
3.1.2 Primitive ABP buffer 28
3.1.3 Extended ABP Buffer 33
3.1.4 Hardware architecture of the ABP buffer 39
3.1.5 Hardware Complexity 41
3.2 Instruction Stream Buffer for VLIW Architectures 42
3.2.1 Design of Instruction Stream Buffer for VLIW Architectures 42
3.2.2 Hardware Design of Instruction Stream Buffer 49
Chapter 4 SWP Communication Schedule 51
4.1. Definitions of Interconnections 51
4.2. Basic Principles of the SWP Scheme 52
4.3 Implementation of the SWP scheme 55
4.4 Mechanism of the SWP Scheme 57
4.5 SWP Scheme Extension for Ring-like Topologies 60
4.6 SWP Scheme for Four-degree Network Topologies 61
4.7 Hardware Implementation and Overhead 64
4.7.1 Head flit switching 64
4.7.2 Forward path and backward path 67
4.7.3 Asynchronous Transceiver Architecture 69
Chapter 5 Analysis of the Effect of the Weighting Factor 76
Chapter 6 Experimental Result 86
6.1 Simulated parameters for arbitration strategies 86
6.1.1 Evaluation of Area and Latency 87
6.1.2 Fairness and Throughput of Arbitration Strategies 89
6.1.3 Effect of the Second Arbitration Strategy 93
6.2 Simulated experiment for Buffering mechanism 95
6.2.1 ABP buffer 95
6.2.2 Simulated parameters for buffering mechanisms of VLIW 101
Chapter 7 Conclusions 104
Bibliography 107
Appendix A 120
A.1 Introduction 120
A.2 Previous Works 122
A.2.1 The problem of the priority encoder 123
A.2.1.2 Relative Works 123
A.3 Balanced Propagation Path for Priority Policy Selector 125
A.3.1 Proposed Priority Encoder Scheme 126
A.3.2 Analytical Latency 132
A.3.3 A Novel Expression Generation Algorithm 133
A.4 Implemented VLSI Design 135
A.4.1 Design methodology for priority selectors using delayed precharge 135
A.4.2 Propagation delay 137
A.5 Experimental Results 139
A.6 Conclusion 144
Personal Publication 145

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