在本論文我們利用電性分析來研究低溫複晶矽薄膜電晶體(LTPS TFT)應用於系統面板及可撓曲面板由電致劣化(electrical stress)引起的元件劣化機制，其中應用於系統面板部分包含：主動陣列式平面顯示器上開關應用、系統面板上驅動電路應用，及非揮發性記憶體的異常電致劣化現象。
第一部份，我們將探討標準結構及具有金屬遮蔽層結構的低溫複晶矽薄膜電晶體操作在暗態及照光環境下由閘極施加脈衝所引起的電致劣化現象。由實驗結果可知將有兩種競爭機制產生於標準結構薄膜電晶體，當元件處於照光環境下的閘極脈衝電致劣化，劣化機制分別為載子量的增加以及電場的減弱。以上兩種現象可由金屬遮蔽層結構的低溫複晶矽薄膜電晶體來驗證，當照光區域為源極/汲極(Source/Drain)端時，元件的劣化機制由電場的減弱所主導;相反地，在通道區域照光時閘極脈衝引起的劣化機制將由載子量的增加所主導。另外，在n型通道元件中由閘極直流偏壓引起的異常驅動電流及次臨界擺幅(subthreshold swing)改善也被討論。此種現象主要是源自於電洞受到閘極角落強電場影響而注入輕摻雜汲極(LDD)上方二氧化矽層(SiO2)。而電洞注入效應將引起有效通道的縮短以及次臨界擺幅的減小。此種強烈的閘極角落電場也藉由模擬軟體 TCAD所成功驗證。
第二部分，我們將討論發生在p型通道低溫複晶矽薄膜電晶體中的異常電容現象。一般薄膜電晶體操作在截止區時之等效電容為閘極與源極/汲極間的重疊電容所並聯。然而實驗中發現此種等效電容會隨量測頻率降低或是量測溫度增加而增加。另外，藉由分析汲極漏電流與電場關係可證明此缺陷輔助汲極端漏電(trap-assisted-gate-induced-drain-leakage)來源為夫倫克爾-普爾發射(Pool-Frenkel emission)及熱場發射(Thermal-Field emission)兩種機制所貢獻。而由電容-電壓(C-V)量測所得到電荷密度變化也符合以上電場關係式;因此可證明在元件中的異常電容現象主要是由汲極端漏電(trap-assisted-gate-induced-drain-leakage)所貢獻。另外，我們成功使用能帶對能帶熱電洞(band-to-band hot electron)注入於閘極與汲極間二氧化矽層(SiO2)以降低垂直電場，進而抑制此種異常電容。
第三部分，為了理解p型通道低溫複晶矽薄膜電晶體操作於照光環境下可靠度行為，我們將討論負偏壓溫度不穩定性(negative bias temperature instability)引起的元件劣化機制與照光效應的關係。由實驗結果可知直流負偏壓溫度不穩定性引起的界面缺陷密度(Nit)與光強度無關;相反地，元件通道中晶界缺陷密度(Ntrap)在照光直流負偏壓溫度不穩定性下操作將比暗態環境嚴重，且劣化程度正比於照光強度。原因可歸咎於照光在通道中引起大量額外電洞，而這些電洞與通道中矽-氫(Si-H)鍵產生化學反應，進而增加晶界缺陷密度(Ntrap)，且此劣化行為增加載子經由缺陷跳躍至價帶(Valance Band)形成漏電流(leakage-current)的機率;想反地，晶界缺陷密度的增加卻可增加載子復和中心而降低元件光漏電流(photo leakage-current)。另外，我們也討論元件操作於動態閘極脈衝下負偏壓溫度不穩定性(negative bias temperature instability)與暫態時間的關係。結果顯示當閘極脈衝上升時間為0.1微秒(μs)時將會增加晶界缺陷密度劣化。主要機制為通道內載子無法追隨閘極脈衝上升時間在通道表面形成反轉層及靜電屏障，因此部分閘極偏壓落入通道造成源極/汲極電洞注入通道區域，進而增加晶界缺陷密度(Ntrap)的劣化。
第四部分，我們研究n型及p型通道低溫複晶矽薄膜電晶體在機械式應力下操作的電性機制。在n型元件中，單軸機械式拉應力可減少電子有效傳輸質量與能谷間散射機率，進而提升元件提升驅動電流。相反地，單軸機械式拉應力對於p型元件而言，卻增加電洞聚積於重電洞(heavy-hole)能帶的機率，進而增加載子有效傳輸質量。此外，我們也研究單軸機械式拉應力對於負偏壓溫度不穩定性的影響。實驗結果顯示由負偏壓溫度不穩定性引起的界面缺陷密度及晶界缺陷密度在機械式拉應力環境操作下都會比無應力下嚴重。藉由萃取能帶密度(density-of-states)及導電活化能(conduction activation energy)發現機械式拉應力增加通道中的扭曲的矽-矽鍵(Si-Si strained-bond)數目，這些扭曲的矽-矽鍵在負偏壓溫度不穩定性操作下容易與解離氫形成反應形成矽斷鍵(dangling-bond)，並增加界面缺陷密度及晶界缺陷密度。
最後，我們將探討應用於非揮發性記憶體的SONOS(Silicon-Oxide-N itride-Oxide-Silicon)電晶體。結果顯示元件操作於在閘極擾動(gate disturb)環境下會造成電子注入於未定義的閘極氧化層區域。此時，這些注入的電子引起在源極/汲極端空乏區，造成電容-電壓(C-V)量測時並聯一空乏電容及電流-電壓(I-V)量測時降低驅動電流。然而，注入在閘極氧化層電子可藉由閘極施加直流負偏壓移除。而發生在未定義的閘極氧化層區域的電場分佈也利用模擬軟體TCAD 加以驗證。

In this dissertation, we investigates the electrical stress induced degradation in low-temperature polycrystalline-silicon thin film transistors (LTPS TFTs) applied for system-on-panel (SOP), including the electrical degradations of device for switch operation in active matrix flat-panel displays, driving circuit and nonvolatile memory. Finally, we also present the reliability of LTPS TFTs applied for flexible displays.
In first part, electrical degradation of conventional and pattered metal-shielding LTPS TFTs under darkened and illuminated dynamic AC stresses are investigated. Experimental results reveal that competitive mechanisms are generated in conventional LTPS TFTs during illuminated stress, namely, carrier increase and electric field weakening. This phenomenon is verified by stressing the patterned source/drain open metal-shielding LTPS TFTs, which determines that the electric field weakening dominates; conversely, the carrier increase is dominated the electrical degradation in channel open metal-shielding device under illuminated stress. In addition, an improvement in anomalous on-current and subthreshold swing (S.S.) in n-channel LTPS TFTs after positive gate bias stress are studied. These improved electric properties are due to the hole trapping at SiO2 above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the S.S.. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above.
Secondly, a mechanism of anomalous capacitance in p-channel LTPS TFTs was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. Besides, by fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and Thermal-Field emission. In addition, the charge density calculated from the Cch-Vg measurement also the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain.
In third part, in order to realize the reliability in p-channel TFTs under illuminated environment operation, the degradation of negative bias temperature instability (NBTI) with illumination effect is investigated. The generations of interface state density (Nit) are identical under various illuminated intensity DC NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap) under illumination was more significant than for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased Ntrap degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region that from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase of Ntrap degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in poly-Si bulk, affecting photosensitivity in LTPS TFTs. Besides, the transient effect assisted NBTI degradation in p-channel LTPS TFTs under dynamic stress is also presented, in which the degradation of the Ntrap becomes more significant as rise time decreases to 1 μs. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant Ntrap increase is assisted by this transient effect.
Fourthly, we study the electric properties of n- and p-channel LTPS TFTs under the mechanical tensile strain. The improved on-current for tensile strained n-channel TFTs is originated form an increase in energy difference between 2- and 4-fold valleys, reducing the inter-valley scattering and further improving the carrier mobility. On the contrary, the hole mobility decreases in p-channel, suggesting the split between the light hole and heavy hole energy bands and an increase in hole population on the heavy hole energy band of poly-Si when the uniaxial tensile strain is parallel to the channel direction. In addition, the Nit and Ntrap degradations induced by NBTI for tensile strained LTPS TFTs are more pronounced than in the unstrained. Extracted density-of-states (DOS) and conduction activation energy (EA) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during the NBTI stress. Therefore, the NBTI degradation is more significant after tensile strain than in an unstrained condition.
Finally, the SONOS-TFT applied to nonvolatile memory is prepared and studied. In the gate disturb stress, a parasitic capacitance and resistance in off-state region are identified as electrons trapped in the gate-insulator (GI) near the defined gate region. Meanwhile, these trapping electrons induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

Chinese Abstract…………...………………...…………...i
English Abstract…………………………………………..iv
Acknowledgments………………………………………viii
Contents………………………...………….….…..…….....x
Figure Captions…………..……………….………...…...xv
Chapter 1 Introduction
1.1 General Background
1.1.1 Overview of Active Matrix Flat-Panel Displays.....1
1.1.2 Overview of Flexible Displays……………….……..1
1.1.3 Overview of Nonvolatile Memory…………..………2
1.2 Motivation………………….........…………...….……....3
1.3 Organization of the Dissertation………….…..…......4
Chapter 2 Theory of Low-Temperature Polycrystalline-Silicon Thin-Film Transistor and Nonvolatile Memory
2.1 Electric Property in Low-temperature polycrystalline-silicon thin-film transistor
2.1.1Transportation mechanisms in LTPS
TFTs………………..................................………….7
2.1.2 Seto’ model………………….………...………….9
2.2 Methods of Device Parameter Extraction
2.2.1 Determination of the Threshold Voltage....……..13
2.2.2 Determination of the Field-Effect Mobility…...….13
2.2.3 Determination of the Subthreshold Swing….…14
2.2.4 Determination of the ActiveEnergy………..…….15
2.2.5 Determination of the Flat-Band Voltage….…….15
2.3 The Photo Leakage Current Mechanism in LTPS
TFTs..……….................................................................15
2.4 The C-V Characteristics in LTPS TFTs…..…….17
2.5 Mechanism of Negative Bias Temperature
Instability in LTPS TFTs…...…...............................19
2.6 The Strained Mechanism in LTPS TFTs.....……21
2.7 The Electrical Characteristics of SONOS-Type
Nonvolatile Memory
2.7.1 Operation of SONOS-Type Nonvolatile
Memory.......................................................................23
2.7.2 Programming Operation…………………….....…23
2.7.3 Erasing Operation………………………….….…..25
2.7.4 Program disturb………………………...….…..….26
Chapter 3 Electrical Degradation in n- channel Low-
Temperature Polycrystalline-Silicon Thin
Film Transistor under Electrical Stress
3.1Introduction………………………….....….……...…...49
3.2Experiment…………………………………………….50
3.3 Results and Discussion
3.3.1 Electrical Degradation in LTPS TFTs under
Illuminated Dynamic Stress……....…….……..52
3.3.2 Anomalous On-Current and Subthreshold
Swing Improvement in LTPS TFTs under Gate
DC Bias Stress……………………....……..……56
3.4Summary……………………………………………...59
Chapter 4 Anomalous Capacitance in p-channel Low-
Temperature Polycrystalline-Silicon Thin
Film Transistor
4.1 Introduction ……………...………………...………69
4.2 Experiment……………...….…………...…...……….69
4.3 Results and Discussion….………......…………….71
4.4 Summary………………………...…………………...77
Chapter 5 Negative Bias Temperature Instability
Degradation in p-channel Low-Temperature
Polycrystalline-Silicon Thin Film Transistors
5.1 Introduction ………………………………………...86
5.2 Experiment………………………...…………….……87
5.3 Results and discussion
5.3.1 Degradation of LTPS TFTs under NBTI Stress
With Illumination Effect…………………….……89
5.3.2 Transient Effect Assisted NBTIDegradation in
LTPS TFTs under Dynamic Stress……..…….95
5.4 Summary………………….……...……………...…100
Chapter 6 Tensile Strained Effect in p-channel Low-
Temperature Polycrystalline-Silicon Thin-
Film Transistor TFT under NBTI stress
6.1 Introduction…….…..……………….…..…………...116
6.2 Experiment………………..………….…..…………117
6.3 Results and Discussion………………....……......118
6.4 Summary…………………….………………….…..122
Chapter 7 Charge Trapping Induced Parasitic
Capacitance and Resistance in SONOS-
TFTs under Gate Bias Stres
7.1 Introduction ………………….….………………..130
7.2 Experiment………………………………….………131
7.3 Results and discussion……………………....…..132
7.4 Summary……………………………………………135
Chapter 8 Conclusion and Suggestions for Future
Work
8.1 Conclusion……….…...........………………….……140
8.2 Suggestions for Future Work……….............…….143
Reference……………….………...…………………......144
Publication List ……………….........…………………161
Biography………………………………………………..166

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