在本論文中，我們對於高速數位印刷電路板電磁效應作三部份探討：在第一部份，利用時與有限差分法（Finite-Difference Time Domain），研究在動力面（Power Plane）作狹縫切割並用通道連結，對於接地彈跳雜訊（Ground Bounce Noise）所造成的電磁輻射效應的影響。我們發現在雜訊四周切割狹縫可以有效減低雜訊，但是當在狹縫兩邊作通道連結時，將會顯著降低電磁輻射防護效果；第二部分探討在多層印刷電路板中，動力面間雜訊藉由連通柱（Via）耦合的時域與頻域效應。利用在動力面間切割狹縫雖然可以在高頻處有效抑制雜訊耦合效應，但是在低頻處將會激發新的共振模態，利用觀察動力面間的電流分布圖可以幫助我們了解此現象，在最後一部分，我們利用FDTD連結SPICE的模擬方法，可以有效預測主動元件在印刷電路板上所造成的電磁效應。

In this thesis, we study the electromagnetic effect of the high-speed digital PCB in three sections. In first section, based on the FDTD modeling approach, the bridging effect of the isolation moat on the EMI caused by the ground bounce noise is investigated. We find that isolating the noise source by slits is effective to eliminate the EMI, but bridges connecting between two sides of the slits will significantly degrade the effect of EMI protection. In second section, we investigate both in time and frequency domains the power plane noise coupling to signal trace with via transition in multi-layered PCB. Separating the power plane with slits is effective in reducing noise coupling in high frequency but a new resonant mode will be excited at lower frequency. Current distribution pattern of this new resonant mode between the power planes helps us to understand this phenomenon more clearly. In final section, by using FDTD link SPICE method, we can predict the electromagnetic behavior of the PCB with active device effectively.

目錄 i
圖表索引 ii
第一章 緒論 1
1.1 簡介與研究動機 1
1.2 論文大綱 1
第二章 FDTD演算法 3
2.1 從馬克斯威爾方程式到FDTD演算法 3
2.1.1 三維方程式 3
2.1.2 中央差分與Yee演算法 3
2.2 數值穩定 7
2.3 介質處理 7
2.4 波源條件 7
2.5 吸收邊界條件 8
2.5.1 Mur吸收邊界 8
2.5.2 完美匹配層吸收邊界 8
2.6 近場與遠場轉換 10
2.7 集總元件 11
2.7.1 FDTD演算法延伸至電路元件 11
2.7.2 電阻 12
2.7.3 阻抗性電壓源 12
2.7.4 電容 13
2.8 電腦演算法與FDTD方法 13
2.8.1 前置過程 13
2.8.2 進行時間步階 13
2.8.3 紀錄場值 13
第三章 切割電源平面對接地彈跳雜訊的效應 15
3.1 接地彈跳雜訊效應 15
3.2 電源平面切割結構 15
3.3 模擬與量測方法 16
3.3.1 模擬方法 16
3.3.2 電磁輻射量測環境及方法 17
3.4 切割電源平面對電源品質的影響 18
3.5 模態電流 20
3.6 切割電源平面對電磁干擾影響 21
3.7 電容防治探討 22

第四章 四層板中接地彈跳雜訊對連通柱(Via)結構之訊號品質效應 25
4.1 四層板中連通柱結構及效應 25
4.2 以細線演算法分析連通柱結構 26
4.3四層板連通柱結構說明 27
4.3.1 測試結構一：連通柱不連續結構 27
4.3.2 測試結構二：連通柱結構對於接地彈跳雜訊耦合效應 28
4.4 頻域及時域之訊號品質模擬與量測方法 29
4.5 結果與討論 30
4.5.1連通柱不連續結構 30
4.5.2連通柱結構對於接地彈跳雜訊耦合效應 32
第五章 FDTD模擬主動元件 38
5.1高頻主動元件訊號品質與電磁輻射 38
5.2 理論分析 38
5.2.1 等效電流源法 38
5.2.2 等效電壓源法 39
5.3模擬主動元件 41
5.3.1雙載子電晶體(BJT) 41
5.3.2 雙載子電晶體模擬結果 42
5.3.3 場效電晶體(FET) 43
5.3.4 互補式場效電晶體反向器(CMOS Inverter) 45
5.4 CMOS元件接地彈跳雜訊模擬 48
第六章 結論 50
參考文獻 51

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