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博碩士論文 etd-0620116-101925 詳細資訊
Title page for etd-0620116-101925
論文名稱
Title
用於系統晶片有效除錯之多維度簽章壓縮方法
A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
46
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2015-10-23
繳交日期
Date of Submission
2016-07-22
關鍵字
Keywords
多重簽章壓縮方法、系統晶片、簽章追蹤方法
Multiple Signature Compaction Method, Signature Based Tracing Methodology, System-on-a-Chip(SoC)
統計
Statistics
本論文已被瀏覽 5737 次,被下載 95
The thesis/dissertation has been browsed 5737 times, has been downloaded 95 times.
中文摘要
簽章是一種能夠有效減少訊號追蹤量的失真壓縮方法,一般我們會在追蹤的精確度與各種不同簽章產生方法的軟硬體實現成本之間做取捨。本論文中我們首先探討使用簽章作為除錯方法在整體的除錯流程上會有什麼樣的影響,接著我們詳細的討論各種常見的簽章壓縮方法的優點與缺點。然後我們進一步探討結合多種簽章方法作為除錯之用,其對於BCD(錯誤週期密度,本論文中所提出的一種用來衡量追蹤精準度的單位)、壓縮率、別名發生機率以及可能的硬體成本之間的影響與取捨。為了方便進行上述的影響與取捨分析,我們也開發了一套以模擬為基礎的估量工具,這套工具會根據使用者提出的限制要求與需求目標,自動化的向使用者提出符合除錯情境的選項供使用者自行選擇。在這套工具的幫助下,使用者就可以選擇出最適合的簽章除錯設定選項以符合其使用環境與情境。最後,根據上述的情境選項,我們實作了一個具可行性並具有數個除錯設定選項的三維簽章壓縮方法以證明本論文所提出方法之可行性與完整性。
Abstract
Signature is an effective lossy compression method to reduce signal trace size at the possible cost of trace precision and implementation cost for different kinds of signatures to generate. In this paper we first investigate how it actually affects the debug flow when we use signatures, and then we examine the strengths and challenges of some typical signature methods. We then further investigate the possibility of combining multiple signatures together to achieve higher Buggy-Cycle-Density (BCD, a metric we proposed to evaluate the trace precision) along with compression ratio, aliasing probability and possible hardware costs. We also proposed a simulation based estimation tool for user to decide which kind of option and scenario they would like to adopt, according to the constraints and requirements that user wanted to meet. With the estimation tool and conditions user provides, they can select the most suitable options to implement on their system. Finally, fitting in the scenario options we acquired above, we implemented a feasible 3D signature compaction method with various debug configurations to justify our work.
目次 Table of Contents
Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivation and Thesis Organization 4
Chapter 2. Related Work 6
2.1 Signature and its Strength & Challenges 6
2.1.1 Multiple Input Signature Register (MISR) 7
2.1.2 Cycling Register (CR) 8
2.1.3 Diagonal Modulo Signature (DMS) 9
2.1.4 Wild Zig-Zag Signature (WZZ) 10
2.1.5 Pseudorandom Pattern Generator (PRPG) 11
2.2 Conservative Signature Compaction Methods 12
Chapter 3. Multi-Dimension Signature Compaction Method 14
3.1 Overall Debug Flow 14
3.2 Data Organization of Multi-Dimension Signatures 16
3.3 Data Flow of Multi-Dimension Signature Compaction 18
3.4 Hardware Components of Multiple Signature Generation and Comparison 21
Chapter 4. Evaluation of the Multiple Dimension Signature Compaction Method 22
4.1 Motivation of Evaluation and Environmental Setup 22
4.2 Metrics and Cost Models 23
4.3 Evaluation and Experiment Results 24
4.4 Simulation Based Multiple Signature Compaction Method Estimation Tool 27
Chapter 5. 3D Signature Compaction Method Implementing Example 29
Chapter 6. Conclusions and Future Work 32
6.1 Conclusions 32
6.2 Future Work 33
Chapter 7. References 35
參考文獻 References
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[2] Ehab Anis and Nicola Nicolici, “Low Cost Debug Architecture using Lossy Compression for Silicon Debug”, Design, Automation & Test in Europe Conference & Exhibition, pp.225-230, April 2007
[3] Katoh K., Namba K., Ito H., “A low-area and short-time scan-based embedded delay measurement using signature registers”, 2010 VLSI-DAT, pp.311-314
[4] Z. Zhang, X. Li, X. Li, “Study on Lossless Data Compress-ion Based on Embedded System”, 5th IEEE International Conference on BIC-TA, pp.1225-1230, Sept. 10
[5] Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao and Ing-Jer Huang, “An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 19, NO. 4, pp. 571-584 April 2011
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[7] Sandesh Prabhakar, Rajamani Sethuram, Micheal S. Hsiao, “Trace Buffer-Based Silicon Debug with Lossless Compression”, 24th Annual Conference on VLSI Design, pp. 358-363, Jan. 2011
[8] M. Hansen, H. Yalcin, and J. P. Hayes, "Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering," IEEE Design and Test, vol. 16, no. 3, pp. 72-80, July-Sept. 1999.
[9] ARM, “Embedded Trace Macrocell ETMv1.0 to ETMv3.5 Architecture Specification”, ARM IHI 0014Q (ID101211)
[10] S. Deyati, A. Banerjee, B.J. Muldrey, A. Chatterjee, “VAST: Post-Silicon Validation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests”, 2013 VLSID, pp.314-319
[11] Kwanghyun Kim, Dong Sha Ha and Joseph G. Tront, “On Using Signature Registers as Pseudorandom Pattern Generators in Bulit-in Self-Testing”, IEEE Transactions on Computer-Aided Design, Vol. 7, No. 8, August 1988, pp. 919-930
[12] Min Li and Azadeh Davoodi, “A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug”, DATE 2013, pp. 485-490
[13] Ho Fai Ko and Nicola Nicolici, “Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 2, February 2009, pp. 285-297
[14] Min Li and Azadeh Davoodi, “Multi-Mode Trace Signal Selection for Post-Silicon Debug”, Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, pp. 640-645
[15] Christoph Albrecht (Cadence Berkeley Labs), “IWLS 2005 Benchmarks”, Fourteenth International Workshop on Logic and Synthesis, 8-10 June 2005.
[16] Chris Inacio (The CMU DSP Team), “CMU DSP, The Carnegie Mellon Synthesizable Digital Signal Processor Core”, June 10, 1999
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