本實驗分兩大部分，汲極與閘極的正交疊（Overlap）以及負交疊（Underlap）之電性曲線及其溫度效應。製程中，利用摻雜不同的汲極長度，使其與閘極作交疊結構。
在有Overlap的情況下，不管是Ion或Ioff電流都隨Overlap交疊量而略微相依，且對於溫度較不敏感；在有Underlap的情況下，不管是Ion或Ioff電流，與Underlap交疊量及溫度都很敏感。
而在文中，透過電性曲線以及能帶圖，可以做為輔助解釋這些現象。Overlap時，受Overlap交疊量影響，是因為存在著PN接面，而Overlap交疊量影響了部份阻值改變，使得穿隧處得到的橫向電場變大，導致穿隧電流略為提升，而其溫度略微提升可能是因TAT機制或能隙下降的關係。Underlap時，則受Underlap交疊量影響，是因為Underlap區是一個本質區的參與，載子受Trap影響的路徑增加，造成載子遷移率下降，而升溫後，Trap效應應該要減弱讓電流提升，但卻發現電流衰退的更嚴重，也對Underlap區的長度更敏感，因此推斷，穿隧電流在Underlap區發生複合效應，導致電流降低，而最後穿隧載子全被複合無法到達汲極端，只剩本質空乏區中的生產電流。
從有Overlap結構中，可以得知具多晶矽通道的穿隧電晶體不易受尺寸改變。而有Underlap結構的，因為在汲極與通道接面有本質區的參與，可以有效降低反向偏壓的雙極性電流，但同時也會衰退Ion，且對溫度敏感。

The purpose of the research was to study the drain lapping effect of tunneling field-effect transistors (TFETs) with polycrystalline-silicon (poly-Si) channel.
The transfer characteristics of source to gate overlap 2m and different drain to gate lapping length indicated that overlap is not sensitive to overlap length and measurement temperature. For this reason, the TFETs with poly-Si channel device have strong immunity against the short channel effect.
When the tunneling field-effect transistors reverse turn on, the carrier transport behavior starts with tunneling of channel/drain junction. However, the underlap region of drain to gate builds the intrinsic depletion region between the channel and drain. The underlap structure can reduce the ambipolar current of tunneling field-effect transistors. There are many traps at the poly-Si intrinsic depletion region which make the carrier mobility degradation. By the higher measurement temperature, the transfer characteristics indicated that there is another reason to lead the current decrease obviously. The recombination current is significant effect of this case.
The TFETs with poly-Si channel with lapping structure have potential to study, in order to find the best carrier transport behavior.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
第一章 緒論 1
第二章 文獻回顧 6
2-1 前言 6
2-2 晶粒邊界 7
2-2-1 晶粒介紹 7
2-2-2 晶粒影響與改善 8
2-3 多晶矽薄膜電晶體 8
2-3-1 傳統多晶矽薄膜電晶體（Conventional Thin-Film Transistor, C-TFT） 9
2-3-2 多晶矽穿隧薄膜電晶體（poly-Si Tunnel Thin-Film Transistor, poly-Si T-TFT） 9
2-4 穿隧原理 10
2-4-1 單晶矽穿隧電晶體（Tunnel MOSFET, T-FET） 10
2-4-2 多晶矽穿隧薄膜電晶體（poly-Si Tunnel Thin-Film Transistor, poly-Si T-TFT） 11
2-5漏電流機制 11
2-5-1 多晶矽薄膜電晶體（poly-Si Thin-Film Transistor, TFT） 12
2-5-2 多晶矽穿隧薄膜電晶體（poly-Si Tunnel Thin-Film Transistor, poly-Si T-TFT） 12
2-5-3 生產與複合電流（Generation and Recombination Cuurent） 13
2-6 短通道效應 13
2-7 多晶矽穿隧薄膜電晶體的改善 14
2-8 穿隧電晶體汲極的交疊效應 15
第三章 參數定義及實驗步驟 31
3-1 量測方式及參數定義 31
3-1-1 量測方式 31
3-1-2 交疊長度 31
3-1-3 開啟狀態下的電流（Ion） 32
3-1-4 關閉狀態下的電流（Ioff） 32
3-2 實驗步驟 33
3-2-1 實驗步驟 33
第四章 結果與討論 40
4-1 電性分析與溫度效應 40
4-2 開啟狀態 40
4-2-1 On-State之Overlap效應 41
4-2-2 On-State之Underlap效應 41
4-3 關閉狀態 42
4-3-1 Off-State之Overlap效應 42
4-3-2 Off-State之Underlap效應 43
第五章 結論 51
參考文獻 52

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