本文提出以小波－機率神經網路偵測電力品質干擾事件，包括諧波、電壓驟降、電壓陡昇、電壓閃爍等事件。本文採用的小波－機率網路兩層結構，小波層可直接從時域的失真波形分析並擷取特徵圖樣，藉由機率神經網路圖樣辨識的能力，進一步判定電力品質干擾事件。由於場規劃邏輯閘陣列（Field Programmable Gate Array, FPGA）提供一個可程式化硬體解決之首，藉由FPGA軟體環境利用硬體描述語言來實作演算法之電路。在文中，會先建立演算法中部分數學運算式基本數位電路模組，再以Bottom-Up的設計方式，來完成整個WPN 數位電路。

The paper proposes a model of detection for voltages and harmonics using wavelet-probabilistic network (WPN). WPN is a two-layer structure, containing the wavelet layer and probabilistic network. It uses the wavelet transformation (WT) and probabilistic neural network (PNN) to analyze distorted waves and classify tasks. In this thesis, the field programmable gate array (FPGA) is employed for the hardware realization of WPN. In the implementation process, by the use of the hardware description language, the WPN algorithm has been embedded into the FPGA chip. Firstly, we divide the mathematical formula of basic WPN algorithm into several parts in order to set up each module individually, then we integrate all modules to complete the design of basic WPN algorithm with digital circuits by the bottom-up process.

圖目錄 Ⅲ
表目錄 Ⅵ
摘要 Ⅶ
Abstract Ⅷ

第一章 緒論 1

1-1 研究背景與動機 1
1-2 研究目的與方法 2
1-3 論文內容概述 4

第二章 小波－機率神經網路演算法理論 6

2-1 類神經網路概論 6
2-1-1 類神經網路架構 9
2-1-2 網路架構分類 10
2-1-3 學習策略分類 11
2-2 機率神經網路 12
2-3 小波-機率網路 20

第三章 VLSI為主之FPGA 28

3-1 FPGA硬體架構 28
3-2 晶片設計流程 34
3-3 Verilog 硬體描述語言 37
3-3-1 Verilog設計方法 37


第四章 系統電路設計 41

4-1 算術運算電路設計 41
4-1-1 數值運算表示法 41
4-1-2 加/減法器 43
4-1-3 定點乘法器 44
4-1-4 多重重存式除法器 47
4-1-5 正弦轉換器 50
4-1-6 指數運算器 52
4-2 小波網路模組 54
4-3 機率網路模組 55
4-3-1 隱藏層模組 55
4-3-2 輸出層模組 58
4-4 以ROM為基礎之訓練資料 59

第五章 演算法測試與RTL模擬結果 62

5-1 電力品質干擾事件測試 62
5-2 小波－機率網路演算法強韌度測試 64
5-3 小波模組驗證 66
5-4 機率網路模組驗證 69
5-4-1 隱藏層模組驗證 69
5-4-2 輸出層模組驗證 71

第六章 結論與展望 73

6-1 結論 73
6-2 未來展望 74

參考文獻 75

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