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博碩士論文 etd-0622113-175410 詳細資訊
Title page for etd-0622113-175410
論文名稱
Title
一種連結電路路由器之可構形設計的軟體實作
Software Implementation of a Configurable Design of Interconnection Routers
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
55
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-26
繳交日期
Date of Submission
2013-09-13
關鍵字
Keywords
系統設計、可構形設計、路由器、自動產生
system design, configurable design, router, automatic generation
統計
Statistics
本論文已被瀏覽 5675 次,被下載 606
The thesis/dissertation has been browsed 5675 times, has been downloaded 606 times.
中文摘要
在硬體系統設計的發展程序中,有效的設計整合與設計的再用可以減少系統的開發時程,我們已研究的可構形設計方法是一種支援此種設計能力的做法。在本研究中,我們運用我們的可構形設計方法,針對硬體路由器的設計做可構形設計的設計與實做。我們將路由器設計系統化分割為階層式組成的功能模組單元,並針對各可構形功能模組規畫不同功能特性的參數化模組設計,以形成可構形的單位與組織,並將其分別設計成可構形的單元設計,以形成路由器構形系統的基本單元與組織。設計工程師可根據其特定的路由器系統功能需求,規劃不同的路由器細部功能組成,再將其對應到各組成模組單元的設計參數,以構形產生所需要的路由器設計。在本論文研究中,我們實做路由器組成之各可構形模組的構形設計與組織,並進行各模組構形與路由器整合構形的實驗,以實證其有效達成本研究的目標。
Abstract
In the development process of hardware system designs, effective design integration and design reuse can reduce system development time. Our previous research on configurable design method plays one way to support such design capability. In this research, we apply our configurable design method in designing and implementing configurable design of hardware router designs. We systematically decomposed a router design into a number of hierarchical functional module units. We also designed various parameterized functional designs of different functional characteristics for each kind of configurable module unit. They form basic units and organization of the configurable router design. Design engineers can plan detailed router functional composition according to specific system requirements of router designs. Then, they can map planned design composition onto design parameters of various composed module units and perform the configuration task to generate the required router design. In this research, we implemented configurable designs and organization of configurable module units of router designs. We also performed configuration experiments of module units and integrated routers to validate that the implementation effectively achieves the goal of this research.
目次 Table of Contents
致謝………………………………………………………………………i
摘要………………………………………………………………………ii
Abstract………………………………………………………………….iii
目錄…..…………………………………………………………………..v
圖目錄..………………………………………………………………….vi
第一章 導論………..……………………………………………………1
1.1 研究動機…………………………………………………………………...1
1.2 研究背景…………………………………………………………………...1
1.3 研究目標……………………………………………………………...........2
1.4 論文大綱……………………………………………………………...........2
第二章 路由器構形方法……………………………..…….…...............3
2.1 系統架構………………………………………………………….…............3
2.1.1 模組的設計方式…………………..……….……………..…3
2.1.2 單模組的組合……...…………................. …...…………................4
2.1.3 階層式模組的組合…...…………................. …...…………........…5
2.2 路由器組成分析………………………………………………….…............6
2.2.1 路由器子模組的功能. …...…………................. …...…………....7
2.2.2 子模組組合範例……...…………................. …...…………............8
2.3 構形模型與技術………...…………………………………...….…............11
2.3.1 構形模型. …...………….. …...………….........................................12
2.3.1.1 模型定義腳本…...…………................. …...………...........13
v
2.3.1.2 模型實體腳本…...…………..................................................13
2.3.2 邏輯模型………………...……...…………................. ….....…........14
2.3.2.1 邏輯模型的介面…...………...………….........................…14
2.3.2.1 邏輯模型的介面……...………...………….........................14
第三章 軟體實作設計…………………………………….…...............17
3.1 軟體實作架構………………………………..……………….…................17
3.1.1 輸入埠模型定義腳本…...…………................. …...…………..…17
3.1.2 輸入埠模型實體腳本.. …...…………................. …...…...............19
3.2 路由器構形模型………………………………..…………….…................20
3.3 傳輸器與接收器構形模型………………………………..………….……25
3.3.1 傳輸器. …...…………................. …...…………............................23
3.3.1 接收器. …...…………................. …...…………..............................24
3.4 輸入埠與輸出埠構形模型………………………………..……….............25
3.4.1 輸入埠.. …...…………................. …...………….............................25
3.4.2 輸出埠.. …...…………...………….................…..............................26
3.4.3 輸入邏輯.. …...………….... …...…………......................................27
3.4.4 輸出邏輯. …...……........ …...………….................…....................29
3.4.5 緩衝器.. …...………….................…………................. …...…….....30
3.5 路由模組構形模型………………………………………….…..................31
3.6 交換器構形模型………………………………………..………….............32
3.7 路由器內部連結構形模型……………………………...…………............33
第四章 實驗與評量………………………...….....................................36
4.1 實驗規劃……………………………...………….........................................36
4.1.1 2x2路由器…...…………....................………………….............36
4.1.2 nxn 路由器... …...…………................. …...…………...............37
vi
4.2 2x2 路由器實驗……………………………...…………..............................43
4.2.1 外部控制衝突避免的2x2 路由器…………………………………..39
4.3 nxn 路由器實驗……………………………...…………..............................42
第五章 結論……………………..……………...…………...................44
參考資料………………………………..…...………….........................45
參考文獻 References
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[8]林灶生,Verilog FPGA晶片設計, 修訂版, 11月97年
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