本論文採用TSMC 90nm製程技術，分析並實作一個10位元、250MS/s取樣速率的兩級管線式類比數位轉換器，並致力於降低功率的虧損。第一級使用二元搜尋式類比數位轉換器完成前5位元資料轉換，提高整體轉換速率；第二級使用連續漸進式類比數位轉換器作為子類比數位轉換器，提高整體架構的精確度，並搭配雙通道分時並行式的概念，將第二級轉換速度提升，完成整體的10位元輸出。

　　二元搜尋式類比數位轉換器使用參考電壓預測機制，有效減少比較器數量，進一步減少晶片面積。第二級類比數位轉換器以bit-by-bit的方式接收第一級比較之結果，並直接切換對應之電容，此方法可加快電容切換的穩定時間，並減少settling error的發生。在連續漸進式類比數位轉換器中，提出LSB電容採用半參考電壓的方法，相較傳統架構減少75%的總電容值，減小晶片面積及降低整體功率消耗。

This thesis presents the architecture of a 10-bit 250-MS/s two-step pipelined analog-to-digital converter for reducing power consumption in TSMC 90nm CMOS technology. The first stage is implemented with a 5-bit binary search ADC to increase conversion speed. The second stage is built with SAR ADC which can enhance the accuracy of the entire system. In order to achieve high speed of the second stage, a concept of two-channel time-interleaved is adopted.

In BS-ADC, we use the mechanism of predicting reference voltage in switching circuit to reduce the number of comparator efficiently. The 2nd stage ADC receives the result from 1st stage ADC bit by bit and directly switches the matching capacitor. The method can reduce settling time for switching capacitor and lower settling error. In SAR ADC, we proposed a method that connects the bottom of LSB capacitor to half reference voltage. Compared to the conventional architecture, the total capacitance is reduced by 75%. Therefore, it can get the small area and fine power efficiency.

Chapter1 緒論 1
1.1 研究動機與目標 1
1.2 論文章節組織 1
Chapter2 類比數位轉換器的原理與特性參數 3
2.1 類比數位轉換器介紹 3
2.2 類比數位轉換器的特性參數 3
2.2.1 取樣頻率(Sampling Rate) 3
2.2.2 量化誤差(Quantization Error) 4
2.2.3 最小有效位元(Least Signification Bit) 5
2.2.4 單一性(Monotonicity) 5
2.2.5 遺失碼(Missing Code) 5
2.2.6 靜態性能(Static Performance) 6
2.2.6.1 偏移誤差(Offset Error) 6
2.2.6.2 增益誤差(Gain Error) 7
2.2.6.3 微分非線性度誤差(Differential Non-Linearity, DNL) 7
2.2.6.4 積分非線性度誤差(Integral Non-Linearity, INL) 8
2.2.7 動態性能(Dynamic Performance) 8
2.2.7.1 訊號雜訊比(Signal-to-Noise Ratio, SNR) 8
2.2.7.2 訊號雜訊失真比(Signal-to-Noise & Distortion Ratio, SNDR) 9
2.2.7.3 無寄生動態範圍(Spurious Free Dynamic Range, SFDR) 9
2.2.7.4 有效位元(Effective Number of Bits, ENOB) 10
2.3 2.3 高速類比數位轉換器架構 10
2.3.1 快閃式類比數位轉換器（The Flash ADC） 10
2.3.2 二元搜尋式類比數位轉換器(The Binary Search ADC) 11
2.3.3 管線式類比數位轉換器(The Pipeline ADC) 12
2.3.4 連續漸進式類比數位轉換器(The Successive Approximation ADC) 13
2.3.5 分行並行式類比數位轉換器(Time Interleaved Parallel ADC) 15
Chapter3 二級管線式類比數位轉換器電路分析與設計考量 17
3.1 低電壓設計考量 17
3.2 取樣保持電路 17
3.2.1 電阻值設計考量 18
3.3 MOS開關 19
3.3.1 開關導通電阻 19
3.3.2 CMOS開關(Transmission Gate) 19
3.3.3 拔靴帶式開關(Bootstrapped Switch) 20
3.3.4 電荷注入效應(Charge Injection) 22
3.3.5 時脈耦合效應(Clock Feedthrough) 23
Chapter4 二級管線式類比數位轉換器之實現 25
4.1 系統架構 25
4.2 第一級之二元搜尋式類比數位轉換器 26
4.2.1 架構介紹 26
4.2.2 Lewis-Gray全差動式動態比較器 29
4.2.3 Switching Network 31
4.3 第二級之雙通道連續漸進式類比數位轉換器 33
4.3.1 傳統全差動式SAR ADC 33
4.3.2 改良式LSB半參考電壓電容陣列 34
4.3.3 Latch-type動態比較器 39
4.3.4 SAR控制邏輯電路 40
4.3.4.1 非同步時脈產生器 41
4.3.4.2 DAC Driver 42
4.4 時脈產生器 46
4.4.1 非重疊時脈產生器 46
4.4.2 雙通道時脈設計 47
Chapter5 效能量測與模擬結果分析 48
5.1 效能量測方法 48
5.1.1 FFT test 48
5.1.2 Histogram test 49
5.1.3 模擬結果與文獻比較 49
5.1.3.1 靜態分析 50
5.1.3.2 動態分析 52
Chapter6 結論與未來展望 55
6.1 結論 55
6.2 未來展望 55
Reference 56

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