本論文提出一個操作在供應電壓1.2V、解析位元10位元、每秒取樣兩億五千萬次之二元搜尋式暨雙通道連續漸進式類比數位轉換器，採用TSMC 90奈米製程技術，可應用於無線通訊系統前端晶片接收端。
在電路設計方面，為達到高取樣速度及低功耗的需求，結合二元搜尋式與連續漸進式類比數位轉換器的優點，將類比數位轉換器分為兩級，第一級為5-bit的二元搜尋式類比數位轉換器，取樣頻率為每秒取樣兩億五千萬次，藉由額外的開關切換所需的參考電壓，可大幅減少比較器之數量，第二級為雙通道5-bit的連續漸進式類比數位轉換器，兩通道之取樣頻率均為每秒取樣一億兩千五百萬次，在二進制電容陣列電路採用直接切換式電容，每進行完一個位元的比較只切換單邊開關，與傳統切換方式相比可減少電容陣列進行切換時的功率消耗，並調整LSB電容之參考電壓，使電容陣列之整體電容值與傳統式相比可減少75%，整體電路採用全差動式設計以減少共模雜訊並增加線性度。

In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt TSMC 90nm process and can be used for receiving in front-end chip of wireless communication system.
In circuit design, we take BS-ADC and SAR-ADC’s advantage for the requirement of high sampling rate and low power consumption and separate ADC in two stages. The first stage is Binary-search ADC which converts high five bit at 250Ms/s sampling rate. Due to additional switching circuit to select correct reference voltage, the need of comparators in BS-ADC can be substantially reduced. The second stage is two-channel SAR ADCs which convert low five bit. Each channel operates at 125Ms/s. In binary-weight capacitor array, we give half-reference voltage for LSB capacitor switching with monotonic switching method. Compared to conventional binary-weight capacitor array, the proposed architecture can reduce total capacitance by 75%. The entire architecture is designed in fully-differential circuit to reduce common mode noise and improve the linearity of the circuit.

目錄
Chapter 1 緒論 1
1.1 動機 1
1.2 論文組織 1
Chapter 2 類比數位轉換器回顧 2
2.1 簡介 2
2.2 類比數位轉換器之參數設計考量 2
2.2.1 靜態性能參數(Static Performance Metrics) 2
2.2.1-1 微分非線性度誤差(DNL) 2
2.2.1-2 整體非線性度誤差(INL) 3
2.2.1-3 偏移誤差(Offset Error) 3
2.2.1-4 增益誤差(Gain Error) 4
2.2.2 動態性能參數(Dynamic Performance Metrics) 5
2.2.2-1 訊號雜訊比(SNR) 5
2.2.2-2 訊號雜訊失真比(SNDR) 5
2.2.2-3 無雜散動態範圍(SFDR) 5
2.2.2-4 有效位元(ENOB) 6
2.3 類比-數位轉換器架構簡介 6
2.3.1 快閃式類比數位轉換器(Flash ADC) 7
2.3.2 管線式類比數位轉換器(Pipeline ADC) 8
2.3.3 連續逼近式類比數位轉換器(Successive Approximation ADC) 10
2.3.4 分時並進式類比數位轉換器(Time-Interleaved ADC) 12
2.3.5 二元搜尋式類比數位轉換器(Binary Search ADC) 13
Chapter 3 類比數位轉換器之設計考量 15
3.1 簡介 15
3.2 取樣保持電路 (Sample & Hold Circuit) 15
3.2.1 MOS開關 (MOS Switch) 16
3.2.1-1 導通電阻 (On Resistor) 16
3.2.1-2 電荷注入效應 (Charge Injection) 18
3.2.1-3 時脈滲入效應 (Clock Feedthrough) 20
3.2.1-4 導通阻值設計 20
3.3 熱雜訊(Thermal Noise) 21
Chapter 4 二元搜尋式暨雙通道連續漸進式類比數位轉換器設計 22
4.1 整體架構 22
4.2 第一級二元搜尋式ADC實行 24
4.3 第二級雙通道連續漸進式ADC實行 25
4.4 DAC電容陣列(DAC Capacitor Array) 26
4.4.1 傳統式二元權重參考電壓電容切換 26
4.4.2 單調式LSB半參考電壓電容切換 29
4.5 DAC開關控制電路 35
4.6 時脈產生器(Clock Generator) 37
4.6.1 非重疊電路(Non-overlapping Circuit) 37
4.6.2 JK型正反器 38
4.7 拔靴帶式開關(Boostrapped Switch) 40
4.8 動態比較器(Dynamic Comparator) 42
4.9 解碼器(Decoder) 45
4.10 SAR 控制邏輯電路(SAR Control Logic circuit ) 46
Chapter 5 模擬結果 49
5.1 5位元BS-ADC 49
5.1.1 靜態參數模擬結果 49
5.1.2 動態參數模擬結果 50
5.2 10位元BS-TISAR ADC 50
5.2.1 靜態參數模擬結果 51
5.2.2 動態參數模擬結果 52
5.3 模擬結果與文獻比較 52
Chapter 6 結論與未來研究方向 57
6.1 結論 57
6.2 未來研究方向 57
參考文獻 58

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