本論文共涵蓋三個不同的主題：第一部份為快速標籤排序器的實作。係根據標籤排序演算法，提出一個硬體上較快速的架構，並將它實際以晶片驗證出來。並且提出只需花很小的硬體成本就可解決偵測排序器狀態的方法。

第二部份為64位元低電晶體數快速動態邏輯比較器的實作。係利用由C.-F. Wu所提出的三種比較器架構之中的兩種來設計一顆64位元比較器，經由晶片實際驗證且解決其原來所無法應付高扇入的問題。

第三部份為工廠電力需量監控系統的實作。這個系統不僅能即時的監視工廠內各迴路的電力使用情形，以圖形介面的方式呈現方便監控人員觀察和操作，並能在電力負載大於預期的情況下，自動將不重要的設施予以卸載。

Three different topics associated with their respective applications are proposed in this thesis. The first application is the implementation of a fast tagged sorter. A novel and high-speed realization of the tagged sorting algorithm is presented. Meanwhile, the problems to detect whether the queue is empty or full is also resolved without increasing any hardware cost.

The second topic is focused on the implementation of a fast dynamic 64-bit comparator with small transistor count. The entire 64-bit comparator is composed of equality comparators and zero/one detectors, which are proposed by C.-F. Wu. The problem to handle a large fan-in requirement is also resolved in our design.

The third topic is to carry out a power demand monitor system for factories. Not only can it monitor the factory’s power network with a graphical user interface, but also can turn off the unessential equipments automatically when the total power consumed by the factory is larger than what was expected.

摘要 i
Abstract ii
第一章 簡介 1
1.1 論文動機與目的 1
1.2 論文大綱 2
第二章 可使用於 100/10 Mbps 路由器之快速標籤
排序器 4
2.1 簡介 4
2.2 研究動機 4
2.3 標籤排序演算法 5
2.3.1 基本排序單元 5
2.3.2 如何保證先進先出（FIFO）的次序 8
2.3.3 偵測排序器的狀態 11
2.4 Moore排序器演算法的實作 14
2.4.1 Moore所提的硬體架構 14
2.4.2 我們所提的硬體架構 15
第三章 低電晶體數動態CMOS的64位元快速比
較器 25
3.1 簡介 25
3.2 研究動機 25
3.3 架構原理與電路設計 26
3.3.1 相同比較器(Equality Comparator) 27
3.3.2 零一偵測器(Zero/One Detector) 28
3.3.3 64-bit 比較器設計 29
3.4 64位元比較器模擬與晶片測試結果 31
3.5 結論 33
第四章 工廠電力需量監控系統 40
4.1 簡介 40
4.2 研究動機 40
4.3 電力需量監控系統之架構 41
4.4 系統設計師 41
4.4.1 設計師操作畫面說明 42
4.4.2 單線圖設定 43
4.4.3 電表資料設定 44
4.4.4 單線圖之電表量測值顯示設定 45
4.5 需量監控程式 47
4.5.1 需量控制曲線 48
4.5.2 系統單線圖 51
4.5.3 年日月報表列印 52
4.5.4 尖離峰設定 54
4.6 DM2436A電表與電表通訊程式 55
4.6.1 DM2436A電表 55
4.6.2 電表通訊程式 58
4.7 使用VB設計系統的技巧 59
4.7.1 動態資料交換（DDE） 59
4.7.2 需量圖形繪製 60
第五章 結論 61
參考文獻 63
附錄 67

[1]. C. M. Blair, “Low cost sorting circuit for VLSI,” IEEE Trans. on Circuits and Systems -Ⅰ: Fundamental Theory and Applications, vol. 43, no. 6, pp. 515-516, June 1996.

[2]. S. K. Das, M. C. Pinotti, and F. Sarkar, “Optimal and load balanced mapping of parallel priority queues in hypercubes,” IEEE Trans. on Parallel and Distributed Systems, vol. 7, no. 6, June 1996.

[3]. Y.-C. Lin, “On balancing sorting on a linear array,” IEEE Trans. on Parallel and Distributed Systems, vol. 4, no. 5, pp. 566-571, May 1993.

[4]. S. W. Moore, and B. T. Graham, “Tagged up/down sorter - a hardware priority queue,” The Computer Journal, vol. 38, no. 9, pp. 695-703, Sep. 1995.

[5]. D. Picker, and R. D. Fellman, “A VLSI priority packet queue eith inheritance and overwrite,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 2, pp. 245-252, June 1995.

[6]. G. V. Russo, and M. Russo, “A novel class of sorting networks,” IEEE Trans. on Circuits and Systems - Ⅰ : Fundamental Theory and Applications, vol. 43, no. 7, July 1996.

[7]. C.-C. Wang, and I.-H. Horng, “Realization of bidirectional associative memory using a pseudo-parallel searching approach,” 1995 IEEE International Conference on Neural Networks, vol. 3, pp. 1502 - 1507, Dec. 1995.

[8]. C.-C. Wang, and G.-C. Lin, “VLSI implementation of a word-slice pipelined maximum selector for priority queues,” 1997 Inter. Symp. on Communications (ISCOM'97), pp. 409-412, Dec. 1997.

[9]. E. Horowitz, S. Sahni, and S. A. Freed, “Fundamentals of Data Structrues in C,” Reading : W. H. Freeman, 1993.

[10]. The ATM Forum, ATM User-network Interface Specification, Prentice-Hall, 1993.

[11]. C.-C. Wang, H.-L. Wu, and S.-K. Huang, “A fast tagged sorter used in 100/10 MBps routers,” 2000 International Conference on Consumer Electronics, (accepted, no. 4017).

[12]. C.-F. Wu, C.-C. Wang, Y.-L. Tseng, and C.-H. Kao, “Design of fast dynamic CMOS comparators with fewer transistor count,” Proceedings of 1998 International Conference on Computer Systems Technology for Industrial Applications-Chip Technology,” pp.167-173, April 1998.

[13]. A.-J. van de Goor, “Testing semiconductor memories theory and practice,” Reading : John Wiley & Sons, 1996.

[14]. M. Afghahi, “A robust single phase clocking for low power, high-speed VLSI applications,” IEEE J. of Solid-State Circuits, vol. 31, no. 2, pp. 247-253, Feb. 1996.

[15]. L. T. Clark and G. F. Taylor, “High fan-in circuit design,” IEEE J. Solid-State Circuits, vol. 31, no. 1, pp. 91-96, Jan. 1996.

[16]. C.-C. Wang, C.-F. Wu, and K.-C. Tsai, “A 1.0 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking,” IEE Pro-ceedings – Computers and Digital Techniques, vol. 145, no. 6, pp. 433-436, Nov. 1998.

[17]. C.-C. Wang, H.-L. Wu, and C.-F. Wu, “A fast dynamic 64-bit comparator with small transistor count,” International Symposium on Circuits and Systems 2000, (accepted, no. 190).

[18]. Visual Basic 5 程式設計經典, pp. 686-693, 1997.

[19]. Microsoft Visual Basic 5 視窗程式設計經典-技巧篇, pp.3-84 至 3-87, 1997.