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博碩士論文 etd-0623103-171714 詳細資訊
Title page for etd-0623103-171714
論文名稱
Title
高靈敏度CMOS電壓對頻率轉換器與靜態式記憶體用高速電流式感測放大器
High Sensitivity CMOS Voltage-to-Frequency Converter and High-Speed Current-Mode Sense Amplifier for SRAMs
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
73
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2003-06-03
繳交日期
Date of Submission
2003-06-23
關鍵字
Keywords
電流式、電壓頻率轉換器、感測放大器、電壓式視窗比較器
Voltage-to-Frequency Converter, Sense Amplifier, Voltage Window comparator, Current-Mode
統計
Statistics
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中文摘要
在本論文的第一部份我們提出了一個全新的電壓頻率轉換器以提供較高的靈敏度。這個電壓頻率轉換器包括一個電流鏡,一個電流乘法器,與一個電壓式視窗比較器。我們所提出的電壓頻率轉換器隨著內建的電容所存的電荷而變動。電壓式視窗比較器靠著電容器的電荷大小已判斷出輸出的準位為高或低。在最差的情況下,我們所提出的電壓頻率轉換器的輸出頻率範圍在0~55 MHz,輸入的控制電壓範圍在0~0.9 V。當功率是0.218 mW時線性度的錯誤率小於9%。
第二個題目中我們提出了一個全新的CMOS電流式高速感測放大器。所提出的感測放大器是由堆疊一級電壓式放大與一級電流式放大所組成。電流式感測器具有很小的輸入阻抗,可以減緩SRAM晶胞的位元對負載的影響,以提高感測的速度。電壓式的感測放大器作為將邏輯準位提高至完全擺幅的狀態。本設計中當輸出負載為1 pF時最差的存取時間是小於1.26 ns。當本設計運作在793 MHz時的功率損耗為0.835 mW。

Abstract
The first topic of this thesis is to propose a novel voltage-to-frequency converter (VFC) to provide high sensitivity. The VFC circuit is composed of one current mirror, one current multiplier, and voltage window comparators. The proposed VFC tracks the variations of the stored charge of a built-in capacitor. The voltage window comparator monitors the voltage of the capacitor to determine whether the output is pulled high or pulled down. The worth-case linear range of the output frequency of the proposed VFC is 0 to 55 MHz provided that the input voltage is 0 to 0.9 V. The error is less than 9% while the power dissipation is 0.218 mW.
The second topic is to carry out a novel CMOS current-mode high- speed sense amplifier (SA). The proposed SA is composed by cascading a current-mode sense amplifier and a voltage-mode sense amplifier. The small input impedance of the current-mode amplifier alleviates the loading effect on the bitlines of SRAM cells such that the sensing speed is enhanced. The voltage-mode amplifier is responsible for boosting the logic levels to full swing. The worst access time of the proposed design is found to be less than 1.26 ns with a 1 pF load on outputs. The power dissipation is merely 0.835 mW at 793 MHz.

目次 Table of Contents
摘要 i
Abstract ii
第一章 簡介 1
1.1 前言 1
1.2 先前文獻探討 2
1.2.1 相關電壓頻率轉換器架構 2
1.2.2 相關感測放大器架構 3
1.3 論文目的 4
1.4 論文大綱 5
第二章 電壓頻率轉換器之相關架構與發展 6
2.1 簡介 6
2.2 電壓頻率轉換器之工作原理與特性 6
2.2.1 工作原理 6
2.2.2 特性 7
2.3 現有相關研究與發展 8
2.3.1 電壓源飄移問題 8
2.3.2 現有相關架構分析 9
2.4 結論 10
第三章 高靈敏度低成本之電壓頻率轉換器 11
3.1 簡介 11
3.2 電壓頻率轉換器工作原理 11




3.3 電路設計  12
3.3.1 電壓頻率轉換器架構說明 12
3.3.2 電壓電流轉換器設計 14
3.3.3 視窗比較器(WC)設計 17
3.3.4 運算放大器設計 20
3.3.5 佈局前模擬結果 22
3.3.6 佈局後模擬結果 23
3.4 晶片量測  24
3.4.1 量測方法與量測儀器 24
3.4.2 預計規格與量測規格 34
3.4.3 晶片佈局圖與照相圖 37
3.5 架構比較  38
3.6 量測後討論與電路改進 39
3.6.1 運算放大器之雜訊考量 40
3.6.2 視窗比較器改進之精確度考量 41
3.6.3 充放電電路改進之精確度考量 45
3.6.4 電壓源雜訊隔絕改進之精確度考量 46
第四章 感測放大器的架構與發展 48
4.1 簡介 48
4.2 感測放大器之工作原理與特性 49
4.3 感測放大器之現有相關研究與發展 50
4.3.1 電壓式與電流式應用趨勢 50




4.3.2 先前架構設計 50
4.4 結論 51
第五章 靜態記憶體用之高速電流感測放大器 52
5.1 簡介 52
5.2 電流式感測放大器工作基本原理 52
5.3 電路設計  54
5.3.1 架構說明 54
5.3.2 電路說明 56
5.3.3 交直流分析 57
5.4 相關模擬與量測考量  60
5.4.1 製程飄移與電壓源雜訊考量 60
5.4.2 不同位元反位元對線上負載與資料輸出變化 61
5.4.3 不同位元反位元對線上負載與感測速度變化 63
5.4.4 量測考量 65
5.4.5 預計規格與架構比較 66
5.4.6 晶片佈局圖 68
第六章 結論與相關成果 69

參考文獻 70
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