本論文包含兩個主題，第一個主題是用於電漿顯示器數位影像處理系統之資料配置器，可以應用在42吋電漿顯示器面板上；第二個主題是低功率小面積之數位輸出入元件。

電漿顯示器數位影像處理系統使用友達光電公司所生產之42吋電漿顯示器面板做為實驗平台，並以場效可程式化邏輯閘陣列(FPGA)作為系統的規劃空間，配合記憶體的使用，可以提供較高的畫面品質及使系統的成本降低。

低功率小面積之數位輸出入元件提出了一個與目前常用的輸出入元件完全不同的概念，主要強調降低功率消耗與縮小面積的使用。該輸出入元件以TSMC 1P5M 0.25μm CMOS製程製作，工作電壓為2.5V，功率消耗減少51.4%，面積減少44%。

This thesis includes two topics. The first topic is a data dispatcher design of a digital image processor for plasma display panels, which can be used in a 42-inch plasma display panel (PDP). The second one is a low-power small-area digital I/O cell design.

The data dispatcher is applied to a 42-inch panel, which is produced by AUO corporation, as a test platform. It comprises FPGAs and RAMs to carry out data dispatching. The solution is verified to provide a better image quality, while the cost is also reduced.

Regarding the low-power small-area digital I/O cell, we propose a totally different concept in contrast to traditional I/O cells. It is focused on low power consumption and small area. The proposed design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The power consumption is measured to be at least 51.4% less than prior works. The area is proven to be at least 44% more efficient.

摘要 i
Abstract ii
第一章 簡介 1
1.1 前言 1
1.2 論文目的 2
1.3 論文大綱 3
第二章 架構介紹與先前文獻探討 4
2.1 電漿顯示器簡介 4
2.1.1 各種顯示器技術簡介 4
2.1.2 電漿顯示器架構介紹 6
2.1.2.1 電漿顯示器之特點 6
2.1.2.2 電漿顯示器發光原理 7
2.1.2.3 電漿顯示器成像原理 10
2.1.2.4 電漿顯示器控制系統 14
2.1.3 研究動機 16
2.2 數位輸出入元件架構介紹 17
2.2.1 數位輸出入元件簡介 17
2.2.2 傳統輸出入元件架構 18
2.2.3 研究動機 20
第三章 電漿顯示器之數位影像處理系統 22
3.1 畫面資料時序及規格 23
3.2 電漿顯示器規格 25
3.3 顯示器資料處理系統(Data Dispatcher) 27
3.3.1 平均影像亮度單元 29
3.3.2 8轉10子圖場之轉換器 31
3.3.3 資料格式轉換 33
3.3.3.1 輸出格式與輸出單元 34
3.3.3.2 資料儲存方式與記憶體模組 37
3.3.3.3 接收PanelLink的資料方式與輸入單元 40
3.3.4 主控單元 42
3.3.5 高壓控制模組 43
3.4 系統實現 44
3.4.1 影像處理系統 44
3.4.1.1 PanelLink介面腳位需求 44
3.4.1.2 記憶體模組腳位需求 45
3.4.1.3 資料積體電路輸出腳位及其他需求 48
3.4.1.4 場效可程式化邏輯閘陣列的選擇 49
3.4.2 記憶體模組 49
3.4.3 高壓控制模組與印刷電路板 50
3.5 系統製作結果 52
3.5.1 場效可程式化邏輯閘陣列的限制 52
3.5.2 記憶體模組電路板的設計不良 53
3.5.3 其他硬體上的設計不良 54
3.5.4 結論 54
3.6 結論與改進 55
3.6.1 結論 55
3.6.2 系統改進 56
第四章 低功率小面積之數位輸出入元件 57
4.1 數位輸出元件架構 57
4.2 數位輸入元件架構 62
4.3 晶片模擬結果 64
4.4 預計規格 67
4.5 測試考量與佈局 70
4.5.1 模擬測試 70
4.5.2 晶片實體測試 70
4.6 晶片實測結果 71
4.6.1 輸出單元的量測結果 73
4.6.2 輸入單元的量測結果 73
4.7 結論與改進 78
第五章 總結與相關成果 80
參考文獻 81
附錄 Data Dispatcher之Verilog code 84

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