本論文包含兩個主題，第一個主題使用動態門檻電壓線字元電晶體之靜態隨機存取記憶體，其特點著重於高速應用。第二個主題討論適用於快閃記憶之高電壓產生電路，作為讀寫與驗證時字線驅動之用。

使用動態門檻電壓線字元電晶體之靜態隨機存取記憶體，主要擷取低門檻電壓的大電流優點，來加速記憶體的操作時脈，並結合高門檻電壓的低漏電流，可作為栓鎖之優點。所實作的4K位元靜態隨機存取記憶體，其最高操作頻率可達667 MHz，存取時間 (access time) 為2.2 ns，靜態功率消耗為43.6 mW。

適用於快閃記憶體之高電壓產生電路，使用兩個不同的相位之四個時脈，用以產生高電壓電源，提供給快閃記憶寫入和抹除時使用。我們所提出的設計使用TSMC 0.25 um 1P5M CMOS製程，當供應電壓為2.5 V，可產生最高 +11.7 V和 -11.6 V。

This thesis includes two topics. The first topic is a CMOS SRAM using dynamic threshold voltage wordline-transistors, which is focused on high speed applications. The second one is a high voltage generator for FLASH memories. The generated high voltages are applied to the wordline controlled transistors during access and verification operations.

By taking advantage of the large current provided by low Vth and low leakage current provided by high Vth, a CMOS SRAM using dynamic threshold voltage wordline transistors is presented. The design of a 4-Kb SRAM is measured to possess a 2.2 ns access time, and consume 43.6 mW in the standby mode. The highest operating clock rate is estimated to be 667 MHz.

A high voltage generator using 4 clocks with two phases is presented to provide a high voltage supply required by FLASH memories during programming mode and erase mode operations. The circuit is implemented by TSMC 0.25um 1P5M CMOS process. It can provide as high as +11.7 V and -11.6 V by given VDD=2.5 V.

摘要 i
Abstract ii
圖目錄 vi
表目錄 ix
第一章 簡介 1
1.1 研究動機 1
1.2 相關先前文獻探討 2
1.3 論文大綱 4
第二章 使用動態門檻電壓線字元電晶體之靜態隨機存取記憶體 5
2.1 概論 5
2.2 架構簡介 7
2.2.1 記憶體單元分析 8
2.2.2 漏電流分析 10
2.2.3 新式記憶單元架構 10
2.2.4 效能比較 11
2.2.5 記憶體單元穩定度分析 17
2.2.6 記憶體單元佈局圖與面積比較 20
2.2.7 Latch-up考量 21
2.3 模擬結果 23
2.3.1 記憶體矩陣 23
2.3.2 行/列解碼器 23
2.3.3 自我測試電路 23
2.4 模擬結果 27
2.5 操作規格 30
2.5.1 與其他架構比較 31
2.6 測試考量與晶片佈局 32
第三章 適用於快閃記憶體之高電壓產生電路 34
3.1 概論 34
3.2 架構簡介 37
3.3 電路區塊介紹 38
3.3.1 環形震盪器 38
3.3.2 時脈產生器 39
3.3.3 緩衝器和高壓電源 40
3.3.4 電壓泵 43
3.3.5 電壓穩壓器 47
3.4 架構比較 49
3.4.1 佈局驗證模擬波形 54
3.4.2 操作規格 56
3.4.3 晶片佈局 57
3.5 測試結果與討論 59
第四章 結論 65
參考文獻 67

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