在本論文中，我們所考慮的是一個受到瑞雷衰退通道影響的多載波分碼多工系統，在多重接取干擾(multiple-access interference; MAI)增強或是背景雜訊(background noise)下系統效能會降低。已知線性限制性(linearly constrained; LC)反向QR分解(inverse QR-decomposition; IQRD)遞迴式最小平方和演算法(recursive least-square; RLS)可解決此問題。故本論文之目的在實現線性限制性反向QR分解遞迴式最小平方和演算法之系統電路，由於現場可程式閘陣列(FPGA)提供一個可程式化硬體解決之首，本論文將藉由FPGA軟體環境利用硬體描述語言來實作演算法之電路。
在LC-IQRD演算法電路設計主要分為兩部分︰一為反向QR分解電路設計，傳統式反向QR分解之電路設計是利用心臟式收縮陣列(systolic array)的方式來實現。心臟式收縮陣列(systolic array)架構其優點在於使電路元件設計模組化，提升電路之執行效率。從電路的角度來看，我們希望把傳統所提出之反向QR分解設計的方式在電路執行上能夠減低電路運算時間。因此，本文提出改良式反向QR分解之電路設計來改善電路之執行效能，其亦擁有元件模組化及縮短電路執行時間之特色。本論文將反向QR分解之電路面積縮小，使反向QR分解電路與演算法後半段電路同時工作，以提升電路運作效率。另外針對後半段演算法電路設計，本論文以元件面積與速度為考量，以加法替代減法的動作，將乘法與加法的運算次數減少，以降低電路設計之複雜度。
在電路設計上其Verilog硬體描述語言規劃上是採取模組化的方式，將演算法拆解成許多獨立的方塊，之後再將各模組加以組合即構成完整的演算法系統電路。由Matlab產生測試信號源，以位元錯誤率(bit error rate; BER)，輸出訊號對干擾加雜訊比(signal to interference and noise ratio; SINR)之效能圖來驗證電路功能。使用Quartus II 軟體，以EP20k1500EFC-33來合成演算法電路，演算法以30bits之定點設計共使用了51536個LE (Logic element)。

In this thesis, the multi-carrier (MC) code division multiple access (CDMA) system in Rayleigh fading channel is considered. The system performance will be degraded due to multiple access interference (MAI) or background noise. It is know that linearly constrained inverse QR-decomposition (LC-IQRD) recursive least-square algorithm can overcome the problems. The main concern of this thesis is to implement the circuit of LC-IQRD algorithm. FPGA components and sets up a high efficient programmable hardware module. In this thesis, we implemented the circuit of LC-IQRD algorithm via a chip of Field Programmable Gate Array (FPGA) with Verilog HDL.
The conventional IQRD circuit design employs systolic array architecture. The advantages of systolic array architecture include modularity and hardware simplicity. These properties are extremely desirable for VLSI implementation. In fact, we expect to reduce the execution time of the conventional IQRD algorithm circuit design. Therefore, in this thesis a modified IQRD circuit design is proposed to improve the effect of circuit implementation. It also has advantage of modularity and reduces the execution time. In order to degrade complexity of LC-IQRD algorithm circuit design, the area and speed of circuit are the consideration in this thesis. The data source is produced by Matlab software. We verify the performance of the system in terms of BER (bit error rate) and SINR (signal to interference and noise ratio).Finally, LC-IQRD algorithm circuit is realized in the Altera EP20k1500EFC-33 chip and on the Quartus II of Altera. The algorithm circuit uses 51536 logic elements (LE) for 30 bits fixed point design.

誌謝 i
中文摘要 ii
英文摘要 iii
目錄 iv
圖表目錄 vi
第一章 簡介 1
第二章 系統架構與原理
2.1 簡介 3
2.2多載波分碼多工接收端系統架構 4
2.3限制性反向QR分解遞迴式最小平方和演算法 7
第三章 系統電路設計
3.1 簡介 14
3.2 FPGA之介紹 14
3.3數學運算功能之電路設計 15
3.3.1數值運算表示法 15
3.3.2加法器與乘法器之電路設計 17
3.3.3結合開根號與除法之電路設計 20
3.3.4矩陣運算之簡化 21
3.4演算法系統電路設計 22
3.4.1反向分解之電路設計 22
3.4.1.1傳統反向QR分解之電路設計 22
3.4.1.2改良反向QR分解之電路設計 29
3.4.2限制性反向QR分解遞迴式最小平方和演算法後半段公式之簡化 33
3.4.3電路運作與驗證流程 43
第四章 電路模擬分析與結論 45
參考文獻 50

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