本論文的題目為適用於數位電視地面廣播系統( digital video broadcasting over terrestrial, DVB-T )之數位接收前端( digital front end, DFE)系統。DVB-T數位電視廣播系統與一般的數位通訊傳輸系統相似，可以大概分成兩個大部份，為通道編碼/解碼 (channel coding/decoding)及調變/解調變(modulation /demodulation)。本論文主要針對DVB-T數位電視廣播系統中接收端的解調變部分，以及一個完整處理的數位接收前端系統之整合。其中主要的運算處理器，2K/8K模式快速傅立葉轉換處理器( 2K/8K Dual-Mode FFT Processor)，已經採用TSMC( Taiwan Semiconductor Manufacturing Company ) 0.35 um 2P4M CMOS製程，來驗證模擬結果。

The topic of this thesis presents a digital front end (DFE) of the digital video broadcasting over terrestrial (DVB-T). The DVB-T system is similar to most of the prior digital communication system. It is roughly divided into two major parts, one for channel coding/decoding, and the other for modulation/demodulation. The thesis is mainly focused on the DVB-T digital video broadcasting demodulation part of the receiver and the integration of a complete digital front demodulation system. The major operational processor of the DFE is a 2K/8K dual-mode FFT processor, which has been implemented by the TSMC ( Taiwan Semiconductor Manu-facturing Company ) 0.35um 2P4M CMOS process technology to justify the simulation results as well as the correctness of the proposed architecture.

摘要 i
Abstract ii
第一章 前言與簡介 1
1.1 前言 1
1.2 DVB-T電視廣播系統相關技術討論 2
1.3 論文目的 4
1.4 目前相關發展 6
1.5 論文大綱 6
第二章 數位I/Q分離器 8
2.1 I/Q分離器簡介 8
2.2 I/Q分離原理 8
2.3 I/Q分離器實作用 10
2.4 模擬結果 12
第三章 雙模2K/8K模式快速傅立葉轉換處理器 14
3.1 簡介 14
3.2 快速傅立葉轉換原理 14
3.3 2K/8K模式FFT架構 15
3.4 模擬與硬體實現 20
3.5 晶片實測結果 23
第四章 時間、頻率及通道的修正與同步以及QAM與AGC 27
4.1 簡介 27
4.1.1 時間同步修正與頻率同步修正簡介 27
4.1.2 通道估測與修正簡介 28
4.1.3 QAM與AGC簡介 29
4.2 原理分析 29
4.2.1 用於時間與頻率同步修正的原理 30
4.2.2 通道估測與修正簡介 31
4.2.3 QAM與AGC原理分析 33
4.3 系統硬體實作 34
4.3.1 系統時間與頻率同步修正實作 34
4.3.2 通道估測與修正實作 37
4.3.3 QAM與AGC硬體實作 38
4.4 模擬與驗證 39
4.4.1 同步電路模擬與驗證 39
4.4.2 QAM與AGC模擬分析 41
第五章 結論與相關討論 43
5.1 結論 43
5.2 DFE系統模擬 44
5.3 DVB-T系統未來發展與相關討論 46
參考文獻 47

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