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博碩士論文 etd-0623109-111336 詳細資訊
Title page for etd-0623109-111336
論文名稱
Title
複晶矽薄膜電晶體應用於系統面板之電性與可靠度研究
Electrical Properties and Reliability of Poly-Si TFTs for System On Panel Application
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
161
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2009-06-13
繳交日期
Date of Submission
2009-06-23
關鍵字
Keywords
複晶矽、薄膜電晶體
TFT, Si, Poly-Si, Reliability
統計
Statistics
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The thesis/dissertation has been browsed 5744 times, has been downloaded 1729 times.
中文摘要
在此論文中,我們研究複晶矽薄膜電晶體於系統面板應用上的電性與可靠度。大致來說,可以把此論文粗略的分成兩個部分。第一個部分為N型薄膜電晶體,我們研究其在交流操作下的劣化特性。另一個部分為P型薄膜電晶體,主要的研究目標為其NBTI劣化特性。這些研究在MOSFET都有廣泛的探討,但是由於複晶矽薄膜中有大量的晶界,這不但嚴重影響了複晶矽薄膜電晶體的電性也使得其劣化機制變得更為複雜。在此論文中,我們發現了過去a-Si薄膜電晶體以及MOSFET都不曾看過的特殊劣化現象。

在第三章中,我們研究N型薄膜電晶體在交流以及室溫操作下的劣化特性。我們利用高頻的交流訊號來模擬作為驅動電路時的操作情形。在Stress後,我們發現了驅動電流有明顯的下降。但是啟始電壓以及次臨限區域卻沒有任何的變化。另外,從輸出特性曲線中,我們也發現有嚴重的current-crowding的現象。透過升溫的量測,我們漸漸釐清了其劣化機制。

在第四章中,我們研究N型薄膜電晶體作為畫素開關時在交流操作下的劣化特性。我們利用低頻的交流訊號來模擬作為畫素開關時的操作情形。在Stress後,我們先是看到驅動電流以及電子遷移率的上升,之後隨著Stress時間的拉長,我們又看到其電子遷移率嚴重的下降,除此之外,我們也觀察到啟始電壓有往左邊飄移的現象。最後,我們釐清了前期與後期的劣化機制。

第五章,我們研究P型薄膜電晶體在交流操作下的劣化特性。我們在閘極給予交流訊號的同時汲極也給予一個15V的偏壓去劣化P型薄膜電晶體。在這個實驗裡,我們發現了一些過去NBTI機制所不能解釋的現象。我們認為這些異常的現象可能與自我加熱效應有關。當P型薄膜電晶體通道內的溫度因為自我加熱效應上升後可能導致Si-H的解離造成了劣化。這樣的劣化我們認為是self-heating induced NBTI effect。
第六章,我們研究非對稱的NBTI劣化。利用正掃與反掃的量測方法,我們發現非對稱的劣化只出現在飽和操作底下。在飽和區的操作下,我們在啟始電壓、驅動電流以及次臨界擺幅的數據中觀察到不對稱的劣化現象。這是因為通道內的垂直電場並不是一個均勻的分佈,而是一個從源極往汲極逐漸強度遞減的分佈,也就是這樣的垂直電場分佈導致了一個非對稱的NBTI劣化造成了上述的劣化現象。
Abstract
English Abstract
In this thesis, we investigate the electrical properties and reliabilities of poly-Si TFTs for system on panel application. Roughly, we divide the thesis into two parts, n-type and p-type TFTs respectively. In n-type TFT, we mainly study degradation characteristics of TFTs under dynamic stress. On the other hand, we focus on special negative bias temperature instability (NBTI) degradation for p-type poly-Si TFTs. Because grain boundary in poly-Si film and serious self-heating effect due to glass substrate, which has a poor thermal conductivity, the electrical properties and reliabilities of poly-Si TFTs become more complicated, compare with metal-oxide-semiconductor field effect transistor (MOSFET). Therefore, in the thesis, we found some strange phenomena never observed in a-Si TFT and MOSFET.

In chapter 3, the degradation mechanism of n-channel poly-silicon thin film transistor (poly-Si TFT) has been investigated at room temperature under dynamic voltage stress, which simulate under high frequency operation as driving devices. The ON-current of TFT is degraded to as low as 0.3 times of the initial value after 1000 second stress. On the other hand, both the sub-threshold swing and threshold voltage kept well during the AC stress. The current crowding effect was rapidly increased with increasing of stress duration. However, comparing the initial and degraded characteristics at rising temperature, namely, 150◦C, the ON-current of TFT only decrease to 75 percent of the initial value after 1000 second AC stress. It depicts that creation of effective trap density in tail-states of poly-Si film is responsible for the electrical degradation of poly-Si TFT. At high temperature, electron has enough energy to pass the energy barrier created by ac stress and the degradation is less obvious.

In chapter 4, the degradation mechanism of n-channel poly-silicon thin film transistor (poly-Si TFT) has been investigated under dynamic voltage stress, which simulate under low frequency operation as pixel switches. Surprisingly, two totally different degradations of TFTs were observed after dynamic stress. Firstly field-effect mobility and driving current increased during early stress. However, a clear and rapid degradation of field-effect mobility occurred instead during later stress. Additionally, the threshold voltage of stressed TFTs strangely shifted to negative direction in later stress, which was never observed in early stress. Finally, we clarify the degradation mechanisms for early and later stress respectively by varied temperature experiments.

In chapter 5, the characteristics of p-type poly-silicon thin film transistor (poly-Si TFT) with dynamic bias stress were investigated. The AC stress is operated with the constant drain voltage (15V) and the varying gate voltage (0V~-15V) to degrade the devices. There are some phenomena which cannot be completely explained by typical NBTI mechanism in the experiment. In addition to NBTI, we suggest that the self-heating effect might be involved, because the self-heating effect could rise channel temperature and cause the dissociation of the Si-H bonds at the poly-Si/SiO2 interface due to the Joule heating. The released hydrogen reacts with SiO2 and causes the fixed charge in the gate oxide. Thus, the degradation of electrical characteristics of device is mainly dominated by the self-heating induced NBTI effect.

In chapter 6, we investigate the asymmetric negative bias temperature instability degradation of poly-Si TFTs. Electric measurements of normal and reverse modes were employed to analyze the degradation on Vt, current, leakage current and sub-threshold swing (S.S.). The results indicated that a non-uniform vertical electric field at the poly-Si/SiO2 resulted in asymmetric negative bias temperature instability degradation. The trap generation was a grading distribution from source to drain. Moreover, some energy diagrams were proposed to explain the experimental data. Sequentially, asymmetric TFT degradation resulted from a grading distribution of trap state induced by asymmetric NBTI.
目次 Table of Contents
Contents
致謝 ii
中文摘要 iv
English Abstract vii
Chapter 1 Introduction
1.1 Introduction 1
1.2 Outline of the thesis 3
1.3 Reference 9

Chapter 2 Poly-Si TFT conduction mechanism and parameter extraction

2.1 Poly-Si TFT transport mechanisms 13
2.2 Method of Device Parameter Extraction 18
2.3 Leakage current 22
2.4 Reference 24
2.5 Figure caption 26

Chapter 3 Thermal Analysis on the Degradation of Poly-Silicon TFTs under AC Stress

3.1 Introduction 30
3.2 Experiment 32
3.3 Results and discussion 33
3.4 Conclusion 40
3.5 Reference 42
3.6 Figure caption 44

Chapter 4 Degradation of poly-Si under dynamic stress with drain bias

4.1 Introduction 60
4.2 Experiment 62
4.3 Results and discussion 63
4.4 Conclusion 69
4.5 Reference 71
4.6 Figure caption 73

Chapter 5 Self-heating effect induced NBTI degradation in poly-Si TFTs under dynamic stress

5.1 Introduction 83
5.2 Experiment 85
5.3 Results and discussion 86
5.4 Conclusion 93
5.5 Reference 95
5.6 Figure caption 99

Chapter 6 Asymmetric negative bias temperature instability degradation of poly-Si TFTs under static stress


6.1 Introduction 115
6.2 Experiment 116
6.3 Results and discussion 117
6.4 Conclusion 125
6.5 Reference 127
6.6 Figure caption 130


Chapter 7 Conclusion 143
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5.4 C. Y. Chen, J. W. Lee, M. W. Ma, W. C. Chen, H. Y. Lin, K. L. Yeh, S. D. Wang, and T. F. Lei, “Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors,” J. Electrochem. Soc., 154, H704-707, 2007
5.5 Chih-Yang Chen, Jam-Wem Lee, Shen-De Wang, Ming-Shan Shieh, Po-Hao Lee, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, and Tan-Fu Lei “Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors” IEEE Trans. Elec. Dev., 53, pp. 2993-3000, 2006.
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6.1 T. Aoyama, K. Ogawa,Y. Mochizuki, and N.Konishi, “Inverse staggered poly-Si and amorphous Si double structure TFT's for LCD panels with peripheral driver circuits integration,” IEEE Trans. Elec. Dev., 43, pp. 701 (1996)
6.2 K. Yoneda, R. Yokoyama, and T. Yamada, “Development trends of LTPS TFT LCDs for mobile applications,” in Proc. Symp. VLSI Circuits, pp. 85–90 (2001).
6.3 H. Tokioka, M. Agari, M. Inoue, T. Yamamoto, H. Murai, and H. Nagata, “Low power consumption TFT-LCD with dynamic memory embedded in pixels,” in Proc. SID, pp. 280–283 (2001).
6.4 C. Y. Chen, J. W. Lee, M. W. Ma, W. C. Chen, H. Y. Lin, K. L. Yeh, S. D. Wang, and T. F. Lei, “Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors,” J. Electrochem. Soc., 154, H704-707, 2007
6.5 Chih-Yang Chen, Jam-Wem Lee, Shen-De Wang, Ming-Shan Shieh, Po-Hao Lee, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, and Tan-Fu Lei “Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors” IEEE Trans. Elec. Dev., 53, pp. 2993-3000, 2006.
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6.12 J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., vol. 53, no. 2, pp. 1193–1202, Feb. 1982.
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6.14 John Y. W. Seto, “the electrical properties of polycrystalline silicon films” J. Appl. Phys. Vol. 46, No. 12, 1975
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