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博碩士論文 etd-0623110-155624 詳細資訊
Title page for etd-0623110-155624
論文名稱
Title
低溫複晶矽薄膜電晶體與非揮發性記憶體之薄膜電晶體其電性分析研究
Electrical mechanism on Low Temperature Polycrystalline Silicon TFT and Nonvolatile memory TFT
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
118
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2010-06-17
繳交日期
Date of Submission
2010-06-23
關鍵字
Keywords
異常電容、閘極偏壓引發汲極端漏電、薄膜電晶體
anomalous capacitance, TFT, GIDL
統計
Statistics
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中文摘要
在此論文中,我們探討低溫複晶矽薄膜電晶體(LTPS TFTs)以及非揮發性記憶體之薄膜電晶體(Nonvolatile memory TFTs)電性分析。

首先我們將先探討分佈於晶界(grain boundary)中的缺陷(trap states)對於電容-電壓特性轉換曲線,由實驗結果可知,晶界中缺陷分佈會影響電容-電壓特性轉換曲線,並且與量測頻率相關。起始電壓(Threshold voltage)的變化量將隨頻率及溫度增加而增加。此外,我們發現當低溫複晶矽薄膜電晶體在非導通條件操作下會有異常電容的產生;一般而言,在低溫複晶矽薄膜電晶體中,非導通狀況下的有效電容為閘極(gate)與汲極(drain)端、源極(source)端的重疊面積。然而實驗結果顯示非導通區域的電容隨著量測頻率的下降而上升或者溫度的上升而上升。另外電流-電壓特性轉換曲線方面,藉由非導通區域的漏電流(leakage current)對電場的曲線之斜率與各種載子傳輸機制的理想值比較,可以確定此漏電流的主因為缺陷輔助閘極偏壓引發汲極端漏電(Trap-Assisted-Gate-Induced-Drain- Leakage),主要機制包含了夫倫克爾-普爾發射(Poole-Frenkel emission)和熱離子場發射(thermal field emission)。除此之外,由電容量測推導出電荷密度對電場的曲線以及漏電流對電場的曲線都呈現相同斜率,此結果指出異常電容主要是因為缺陷輔助閘極偏壓引發汲極端漏電所造成的。在此之後,我們使用能帶對能帶的熱電子(band to band hot electron)注入閘極氧化層來降低閘極端到汲極端的垂直電場,進一步抑制此異常電容現象。其垂直電場的變化也由ISE-TCAD 模擬而証實。

除此之外,我們研究n 通道非揮發性記憶體之薄膜電晶體(Nonvolatile memory TFTs)在閘極經過施加直流偏壓電致劣化的機制探討,其閘極絕緣層結構為氧化矽-氮化矽-氧化矽 (Oxide-Nitride-Oxide),記憶體狀態分別在經過抹除及寫入的操作後,持續在閘極施加垂直電場做電致劣化測試,其垂直電場小於抹除及寫入時的垂直電場,分析此垂直電場所造成的擁有記憶體特性的電晶體特性變化。

首先,先對一般結構薄膜電晶體做相同垂直電場電致劣化,實驗結果顯示出除了氧化層缺陷捕獲電子密度(Nox)有明顯的變化,還有些微的介面缺陷能態密度(Nit)產生,而在晶界缺陷能態密度(Ntrap)則沒有明顯的改變,接著由TCAD 模擬驗證,而模擬結果不論是I-V 曲線或者是C-V 曲線都與實驗結果趨勢符合,進而我們更可以確定這些缺陷密度的發生。會產生這些現象主要是因為在垂直電場向下時,由庫倫引力吸引通道電子注入在氧化層缺陷,以及在注入的過程中,破壞介面並產生介面缺陷。

在非揮發性記憶體之薄膜電晶體方面,在閘極施加正垂直電場做電致劣化測試下,不論是未操作過的或者是抹除狀態過的條件都與一般結構薄膜電晶體有相同的現象,而寫入狀態後的非揮發性記憶體之薄膜電晶體則呈現不同的趨勢,主要機制是寫入時補獲在氮化矽的電子降低了電致劣化測試下的電場,因此元件特性並不會隨電致劣化時間增加而有所劣化,而主要機制轉變為氮化矽的補獲電子與閘極的穿遂機制。除此之外,寫入狀態的非揮發性記憶體之薄膜電晶體會明顯的造成非導通區域的電容變化,主要是因為靠近閘極端角落的電場特別強,造成非閘極控制區域的電子額外注入引發額外的空乏電容,我們也會由模擬TCAD 來確認兩端電場的改變。

最後,在未操作過和抹除後的非揮發性記憶體之薄膜電晶體其缺陷輔助閘極偏壓引發汲極端漏電會隨著電致劣化的時間增加而增加,其主要原因是電子大量注入在閘極和汲極/源極之間的重疊的介電層,並在此區引起更嚴重的能帶彎曲形成更大的漏電。相反地,在寫入後的電晶體漏電會隨著時間增加而減少,其主要原因是對於寫入後的電晶體,在介電層過多的電子會因為閘極正偏壓而使其電子往閘極端流失造成漏電下降。
Abstract
In this work, electrical mechanism of Low Temperature Poly-Si Thin-Film Transistors (LTPS TFTs) and Nonvolatile memory TFTs was investigated.

First, relationship between trap states in grain boundary and capacitance-voltage (C-V) transfer characteristic curve would be discussed. The experimental results reveal that the C-V curves were a function with the trap state distribution and the measured frequency. The threshold voltage was increased with increasing measured frequency and temperature. Besides, anomalous capacitance was generated in p-channel LTPS TFTs when the device was operated at off-state. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measured frequency and/or with increasing measurement temperature. By fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and thermal field emission. In addition, the charge density calculated from the Cch-Vg measurement also
the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by ISE-TCAD software.

In addition, the degradation mechanism in Nonvolatile memory TFTs under DC stress was discussed. The gate insulator of the Nonvolatile memory TFTs was stacked with oxide-nitride-oxide and the thickness was
40nm-20nm-10nm, respectively. The polarities of the gate insulator were included fresh state, programmed state and erased state. In order to compare the ONO with the STD TFTs, the STD TFTs was also discussed
with the same DC stress condition. The experimental results reveal that the degradation phenomenon was not only oxide trapping (Nox) but alsointerface trap (Nit). Besides, the simulation software ISE-TCAD was used to demonstrate these results. This main degradation phenomenon was caused by carrier injecting into oxide which was due to the coulomb force. The Nox and Nit were increased while carrier injected into the gate oxide.

On the other hand, there were showed identical degradation mechanism in fresh state and erase state SONOS TFTs under the positive gate bias
stress, but in which were not consistent with the program state. In program state, the vertical electric field was released due to trapping electrons in nitride. Therefore, the electric property would slightly
improve during the positive gate bias stress and the main degradation mechanism was become to the carrier detrapped from nitride to gate terminal.

Beside, the off state C-V curve was slightly increased under the positive gate bias stress in program state. This result was contributed to the electrons trapped in the oxide near the gate insulator edge cause by
the electric field corner effect. And then, the electric field corner effect was also verified by the simulation software ISE-TCAD.

Finally, the TAGIDL in fresh and erase states is increased with increasing the stress time. On contrary, the situation in program state is decreased with increasing the stress time. These results are contributed to a large number electrons injection into the overlapped insulator region between the gate and S/D and enhancing the band bending in the overlapped region when SONOS TFT is operated at fresh and erase states. However, in program state, the electrons trapped in the nitride are flowed to the gate due to the positive bias.
目次 Table of Contents
Content
致謝 _____________________________________________________ 1
中文摘要 _________________________________________________ 2
English Abstract ___________________________________________ 6
Figure Captions __________________________________________ 10
Chapter 1 ________________________________________________ 16
1-1. Overview _____________________________________________________ 16
1-2. Introduction of Trap-Assisted Gate Induced Drain Leakage 20
Chapter 2 ________________________________________________ 22
2-1. Device Fabrication _____________________________________________ 22
2-1-1. Fabrication Processes of LTPS TFT-Si Device _______________________________ 22
2-1-2. Technology of ELA Crystallization ________________________________________ 23
2-1-3. Fabrication Processes of Nonvolatile memory LTPS SONOS TFT Device ________ 25
2-2. Defects in polycrystalline-silicon film _____________________________ 25
2-3. Basic characterization of the LTPS TFT ___________________________ 27
2-3-1. The I-V transfer characteristics ___________________________________________ 27
2-3-2. The C-V transfer characteristics __________________________________________ 29
2-4. Introduction of Seto’s model _____________________________________ 30
Chapter 3 ________________________________________________ 35
3-1. Instruments and measurement setup ______________________________ 35
3-1-1.Instruments ____________________________________________________________ 35
3-1-2.Set up instruments for I-V ________________________________________________ 36
3-2. Methods of Device Parameter Extraction __________________________ 37
3-2-1 Determination of the threshold voltage _____________________________________ 37
3-2-2 Determination of the field-effect mobility ___________________________________ 38
3-2-3 Determination of the subthreshold swing ____________________________________ 39
3-2-4 Determination of on/off current ratio _______________________________________ 40
3-2-5 Determination of the active energy _________________________________________ 41
3-2-6 Determination of density of state __________________________________________ 41
3-2-7 Determination of the trap density __________________________________________ 43
Chapter 4 ________________________________________________ 45
4-1. Motivation I __________________________________________________ 45
4-2. Anomalous C-V for P-channel STD TFT ___________________________ 46
4-2-1 Introduction of C-V for general TFT _______________________________________ 46
4-2-2 C-V study with different temperature and frequency for N-channel STD TFT _____ 46
4-2-3 Usual C-V study and discovery of anomalous C-V for P-channel STD TFT ________ 49
4-2-4 Summary I________ 56
4-3. Motivation II _________________________________________________ 56
4-4. Positive, Negative Bias stress for STD TFT _________________________ 57
4-4-1 Positive Bias stress for STD TFT __________________________________________ 57
4-4-2 Negative Bias stress for STD TFT __________________________________________ 61
4-5. Positive, Negative Bias stress for SONOS TFT ______________________ 61
4-5-1 Positive Bias stress for SONOS TFT ________________________________________ 61
4-5-2 Negative Bias stress for SONOS TFT _______________________________________ 65
4-5-3 Summary II 66
Chapter 5 ________________________________________________ 67
Reference _______________________________________________ 69
Figure Capation __________________________________________ 78
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[4.12] Bias-stress-induced stretched-exponential time dependence of charge injection and trapping in amorphous thin-film transistors
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