金氧半場效電晶體為了達到高效能高經濟效益的目標而隨著摩爾定律(Moore’s Law)微縮，然而單純地微縮尺寸去達成摩爾定律下的演化趨勢已經無法應付90奈米的量產世代，因此需要其他不同的技術來補救微縮下造成的缺點並且提高元件的性能(performance)，包括應變矽(strained-Si)技術提升載子遷移率(mobility)，引入高介電常數金屬閘極(high-k/metal gate)堆疊結構技術降低閘極漏電以及提高驅動電流，或是使用矽覆絕緣(Silicon-on-Insulator, SOI)結構提昇元件切換速度等。但電晶體的性能與可靠度(reliability)是必需權衡(trade off)的議題。因此，在65奈米製程世代之後，不少可靠度的議題被廣泛地討論，包括偏壓溫度不穩定性(bias temperature instability, BTI)，熱載子退化(hot carrier degradation)，或是閘極介電層完整性(Gate oxide Integrity, GOI)的議題等。
本研究針對65奈米的SOI金氧半場效電晶體與28奈米的high-k/metal gate金氧半場效電晶體討論可靠度的議題。針對偏壓溫度不穩定性，在SOI p-MOSFETs上，我們探討了三種變因下的負偏壓溫度不穩定性(negative bias temperature instability, NBTI)，首先我們比較浮體(floating body, FB)元件與標準四端點(body contact, BC)元件的NBTI差異。發現FB元件的退化現象較不明顯，這是因為閘極誘發浮體效應(gate-induced floating body effect, GIFBE)造成閘極氧化層電場下降所導致的。接著施予外界應力(mechanical strain)後，發現FB元件的NBTI劣化變的更加地不明顯。經過研究驗證後，發現為應變導致的能帶窄化增強了碰撞游離率，使得GIFBE造成的電場下降之現象變得更加明顯所致。而第三變因，為施加汲極偏壓下的NBTI現象之討論。我們發現，早先的研究已發現，施加一持續的汲極偏壓會導致汲極端的閘極電場空乏，使得靠近汲極端的NBTI現象較輕微，抑制元件的退化。而我們卻認為尚有其他因素會影響到NBTI，那就是電洞與矽氫(Si-H)鍵的反應過程時間，會因為汲極偏壓所引起的橫向電場使電洞流動，造成通道內的非穩態，導致Si-H鍵斷鍵不完全而抑制了NBTI劣化。利用實驗條件的等效，在施加汲極端的條件下，我們得到了較不嚴重的劣化結果，符合我們提出之假設。接著，我們利用變頻跟變壓的方式去驗證論點，發現汲極偏壓的施加頻率越慢，或是施加偏壓越大，載子受電場牽引的現象越明顯，而調變了NBTI劣化。而high-k/metal gate金氧半場效電晶體的可靠度研究，我們探討了P型元件的正偏壓溫度不穩定性(PBTI)。發現電子捕捉的現象主導了實驗退化的機制，但卻有一異常的charge pumping (CP)訊號產生，經過探討，我們認定為是載子行經SiO2與HfO2介面時發生的碰撞游離，產生介面缺陷，因而被頻率選擇在1 MHz的CP量測到。另一方面，在高溫環境下我們比較了金屬閘極中含氮量多與寡的兩種元件的起始電壓飄移。發現含氮量少的元件，其載子遵守Poole-Frenkle機制，而使得起始電壓飄移量隨著實驗溫度越高而越小。另一方面，含氮量多的元件，則是遵守熱離子發射的機制，因此其起始電壓飄移量隨著溫度越高而越明顯。而可靠度研究的第二部份為熱載子退化(hot carrier stress, HCS)的研究，在SOI n-MOSFET上，我們比較BC與FB兩種元件的退化程度，卻發現了FB的元件退化較明顯。我們推測是浮體效應造成的橫向碰撞游離率的提高。利用快速可靠度量測系統(Fast BTI)，我們偵測到因浮體效應而導致的暫態電流抬升，表示浮體效應能增強電流值而加強碰撞游離的機會。在高溫下的表現，則發現浮體效應加重HCS的現象減輕了，經由實驗驗證，這是由於高溫下活躍的載子複合率所導致的，使得在基板端累積的載子快速地被複合掉，降低了浮體效應。當外界應力引入HCS後，也發現應變導致的能帶窄化能使橫向碰撞游離率提高。基於此，我們去比較應變下的BC與FB的元件退化情形，發現兩者的退化差量差異不大，這是因為雙重效應(應變與浮體)導致碰撞游離的現象變得更加嚴重，使載子在基板端的充電效果到達飽和，載子往源極端導走所致。除此之外，high-k/metal gate p-MOSFETs在HCS下的劣化則是以熱載子被捕捉(charging trapping)於高介電常數膜層端為主要機制，我們提出了載子捕捉誘發汲極電致位障降低(drain-induced barrier lowering, DIBL)的機制來解釋HCS後起始電壓變小的原因。最後，我們探討動態HCS的效應於high-k/metal gate n-MOSFETs。我們將動態HCS的條件區分成on-state與off-state作探討，根據比較的結果，我們發現on-state的條件沒有電洞注入的現像，但是off-state的實驗條件則會有帶隙穿隧熱電洞(band-to-band hot hole)的貢獻於電洞補捉。由CP量測，我們推論在捕捉載子下方主動層區域，會因為庫倫電場的影響而產生一小範圍的本質區(intrinsic region)。使得HCS時，空乏區電場重新分佈。因此，當熱電子在加速的過程中，會因為本質區的產生而導致加速不完全，動能不足，無法產生較能量較深的斷鍵，導致次臨界區劣化不顯著。

This dissertation studies physical mechanisms and reliability analysis on Silicon-on-Insulator (SOI) and high-K/metal gate MOSFETs. For the part of bias temperature instability (BTI), we investigate negative bias temperature instability (NBTI) degradation in partially depleted (PD) SOI p-MOSFETs in three cases including gate-induced floating body effect (GIFBE), mechanical strain, and applied drain voltage We find that FB device shows less degradation than BC device, since GIFBE reduce the oxide electric field during stress. After that, strain-induced band gap narrowing leads NBTI further lowering due to much significant GIFBE. As we applied VD during NBT stress, NBTI-induced Vth shift decrease as VD increase within VD=-1V. Expect depletion, we find VD can shorten the time for reaction between channel holes and Si-H bonds under identical conditions, suppressing NBTI. Beyond VD=-1, higher VD can induce self-heating behavior in SOI devices, and then aggravating NBTI. As well as, we also studies positive bias stress (PBS) in HfO2/TiN p-MOSFETs and its high temperature effect. Electron trapping dominates the degradation under PBS in HfO2/TiN p-MOSFETs. But abnormal interface states generation occurs at HfO2/SiO2 to leads charging pumping (CP) degradation. Under high temperature, different nitrogen (N) concentration in metal gate determines the mechanism of conduction of PBS-induces electron (gate) current. Poole-Frenkel emission dominates the trapping-induced Vth shift in device with much N, but thermionic emission mechanism impacts the trapping-induced Vth shift in device with less N. For hot carrier stress (HCS), we study HCS degradation in PD SOI n-MOSFETs, and explain FB effect can aggravate HCS due to increase in impact ionization rate. However, the impact of FB effect on HCS in PD SOI n-MOSFETs decreases as temperature increases. This is because heavy recombination rate makes body charging behavior to vanish gradually. Additionally, strain effect was introduced into HCS in PD SOI n-MOSFETs. Strain-induced band gap narrowing increases impact ionization rate and HCS degradation. But FB effect under strain shows saturated rapid due to critical body charging behavior and band gap narrowing. Moreover, we propose a mode called charge trapping-induced drain-induced barrier lowering (DIBL) to explain positive Vth shift under HCS in HfO2/TiN p-MOSFETs. For HfO2/TiN n-MOSFETs, it studies dynamic effect in HCS. We find off-state part of stress condition has a contribution as gate-induced drain leakage (GIDL) stress to generate band-to-band hot hole. Thus, we propose that hole trapping can induce a intrinsic region below trapping within active layer. It can make incomplete and discontinued acceleration for channel hot electron, suppressing HCS degradation.

Contents

Abstract (Chinese)……………………………………………………….i
Abstract (English)……………………………………………………….v
Acknowledgements……………………….…………………………...viii
Contents………………………………………………………………….x
Figure Captions….……………………………………………………..xv

Chapter 1 Introduction
1.1 Basic Background………………………………………………………………..1
1.1.1 Overview of Moore’s law, Roadmap of scaling down………………………….1
1.1.2 Overview of Strained-Si (Silicon) Technology…………………………………3
1.1.3 Overview of Silicon-on-Insulator (SOI) MOSFETs……………………………4
1.1.4 Overview of high dielectric constant (high-k)/metal gate MOSFETs…………..6
1.2 Motivation………………………………………………………………………..7
1.3 Organization of Dissertation …………………………………………………….8
Reference……………………………………………………………………………....9

Chapter 2 Electric Parameters and Measurement Techniques
2.1 Extraction of Electric Parameters……………………………………………….19
2.1.1 Determination of threshold voltage (Vth) ……………………………….…….19
2.1.2 Determination of subthreshold swing (S.S) …………………………………..20
2.1.3 Determination of transconductance (Gm) and field-effect Mobility (μFE)……..21
2.2 Measurement Techniques……………………………………………………….22
2.2.1 Charging pumping (CP) Technology…………………………………………..22
2.2.2 Fast I-V Technology…………………………………………………………...23
Reference……………………………………………………………………………..24

Chapter 3 Impact of Gate-Induced Floating Body Effect (GIFBE) on NBTI in Partially Depleted SOI p-MOSFETs
3.1 Introduction……………………………………………………………………..31
3.2 The Mechanism of Negative Bias Temperature Instability (NBTI)…………….33
3.3 Experiment……………………………………………………………………...36
3.4 Result and Discussion…………………………………………………………..37
3.5 Summary………………………………………………………………………..41
Reference……………………………………………………………………………..42

Chapter 4 Impact of Mechanical Strain on GIFBE in PD SOI p-MOSFETs as indicated from NBTI degradation
4.1 Introduction……………………………………………………………………..55
4.2 Experiment……………………………………………………………………...56
4.3 Result and Discussion…………………………………………………………..57
4.4 Summary………………………………………………………………………..60
Reference…………………………………………………………………………….61

Chapter 5 Drain Bias Dependence on NBTI Degradation in PD SOI p-MOSFETs with Ultra Thin Gate Oxide
5.1 Introduction……………………………………………………………………..73
5.2 Experiment……………………………………………………………………...75
5.3 Result and Discussion…………………………………………………………..76
5.4 Summary………………………………………………………………………..82
Reference……………………………………………………………………………..82

Chapter 6 Hot Carrier Degradation in PD SOI n-channel MOSFETs under High Temperature and Mechanical Strain
6.1 Introduction……………………………………………………………………..94
6.2 Experiment………………………………………………………………….…..95
6.3 Result and Discussion…………………………………………………………..96
6.3.1 Hot Carrier Degradation in PD SOI n-channel MOSFETs…………………..96
6.3.2 Hot Carrier Degradation in PD SOI n-channel MOSFETs under High Temperature…………………………………………………………………..98
6.3.3 Hot Carrier Degradation in PD SOI n-channel MOSFETs under Mechanical Strain………………………………………………………………………...100
6.4 Summary………………………………………………………………………103
Reference……………………………………………………………………………104

Chapter 7 Positive Bias Stress-induced Degradation in HfO2/TiN p-channel MOSFETs under High Temperature
7.1 Introduction……………………………………………………………………126
7.2 Experiment…………………………………………………………………….127
7.3 Result and Discussion…………………………………………………………128
7.3.1 Abnormal Interface State Generation under Positive Bias Stress in HfO2/TiN p-channel MOSFETs………………………………………………………..128
7.3.2 Positive Bias Stress-induced Instability in HfO2/TiN p-channel MOSFETs under High Temperature…………………………………………………….133
7.4 Summary………………………………………………………………………135
Reference……………………………………………………………………………136

Chapter 8 Charge trapping-induced Drain-Induced-Barrier Height-Lowering (DIBL) in HfO2/TiN p-channel MOSFETs under Hot Carrier Stress
8.1 Introduction……………………………………………………………………151
8.2 Experiment…………………………………………………………………….153
8.3 Result and Discussion…………………………………………………………154
8.4 Summary………………………………………………………………………159
Reference……………………………………………………………………………159

Chapter 9 Dynamic Hot Carrier Stress in TiN/HfO2 n-channel MOSFETs
9.1 Introduction……………………………………………………………………170
9.2 Experiment…………………………………………………………………….171
9.3 Result and Discussion…………………………………………………………173
9.4 Summary………………………………………………………………………176
Reference……………………………………………………………………………177

Chapter 10 Conclusion and Future Work
10.1 Conclusion …………………………………………………………………….193
10.2 Suggestions for Future Study………………………………………………….197

Publication List……...……………………………………………………………..199
Vita………………………………………………………………………………….202

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