此全數位鎖相迴路(All-Digital Phase-Locked Loop，ADPLL)使用TSMC 90nm製程，採用數位頻率偵測器(Digital Frequency Detector，DFD)和連續逼近暫存器(Successive Approximation Register，SAR)來控制數位控制振盪器(Digitally Controlled Oscillator，DCO)以及一些控制單元(Control Unit)所組成。在全數位鎖相迴路裡，設計數位控制振盪器會是一個關鍵，它將影響整個全數位鎖相迴路的效能。而這部分採用交錯型遲滯延遲元件和控制負載電容的方式，分成6位元粗調和5位元細調來提高頻率的精準度，並且讓數位控制振盪器節省電源，達到降低功耗和面積。另外，在使用傳統式的連續逼近暫存器，將因為在製程、電壓和溫度變異的環境中無法對電路做持續追蹤而造成電路的不正確，而為了避免全數位鎖相迴路死鎖的問題，因此會使用改良式連續逼近暫存器來克服所面臨的問題，讓整個鎖相迴路在鎖定之後能夠持續對電路做追蹤。此全數位鎖相迴路電路的工作電壓為1V，鎖相迴路的輸入參考頻率為20MHz，工作頻率範圍為201MHz~1.19GHz，在500MHz操作下之功率消耗為0.266mW，時脈抖動模擬分別在500MHz為101.1ps和1GHz為39.9ps。

This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as some control units. Digitally controlled oscillator is the key component of performance. The performance of digitally controlled oscillator affects the performance of the whole circuit. The part of digitally controlled oscillator uses the interlaced hysteresis delay cell and digitally controlled varactors. It is divided into the coarse-tuning stages and the fine-tuning stages are 6-bit and 5-bit period control code respectively. The digitally controlled oscillator has low power consumption, small area and high resolution. In addition, the ADPLL will go unlocked in the face of process, voltage, and temperature (PVT) variations when it uses a conventional successive approximation register. We will use an improved successive approximation register to overcome the problem of dead lock. By this design, the ADPLL can be monitored continuously. The supply voltage is 1 V. The reference frequency is 20 MHz. The output frequency can achieve from 201 MHz to 1.19 GHz. The power consumption is 0.266 mW at 500 MHz. The simulation of the jitter is 101.1 ps at 500MHz and 39.9 ps at 1 GHz.

第1章 緒論 1
1.1 研究動機 1
1.2 論文組織架構 2
第2章 鎖相迴路基本觀念 3
2.1 鎖相迴路種類簡介 3
2.2 鎖相迴路基本架構 3
2.3 類比式鎖相迴路 5
2.4 數位式鎖相迴路 7
2.5 全數位式鎖相迴路 10
2.6 數位控制振盪器 12
第3章 全數位式鎖相迴路之設計 16
3.1 系統架構 16
3.2 數位頻率偵測器 17
3.3 控制單元 21
3.3-1 連續逼近暫存器 21
3.3-2 連續逼近暫存器具有持續追蹤機制 23
3.4 數位控制振盪器 25
3.4-1 延遲元件 27
3.4-2 突波預防單元 29
3.5 除頻器 31
第4章 模擬結果 32
4.1 數位頻率偵測器模擬 32
4.2 連續逼近暫存器模擬 33
4.3 連續逼近暫存器具有持續追蹤模擬 34
4.4 數位控制振盪器模擬 35
4.5 全數位鎖相迴路模擬 39
4.6 時脈抖動模擬(peak-to-peak jitter) 40
4.7 電路規格與比較 41
第5章 結論與未來研究 43
5.1 結論 43
5.2 未來研究 43
參考文獻 44

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