電力線通訊(Power Line Communication, PLC)為當今主要的有線網路之一，其想法為將原本用來傳輸能量的電力線，利用正交分頻多工(Orthogonal Frequency-Division Multiplexing, OFDM)的調變方式將資訊載到電力線，而在無線通訊非常普遍的今日，電力線還是具有不可取代的特性，因其不再需要重新佈線，且絕大部分的地區皆具有電力，而電子設備又可與電力線緊密的結合在一塊，因此造就了其涵蓋率非常寬廣的特性。
本篇論文研究的方向為電力線通訊中的HomePlug AV標準規格，在系統架構上HomePlug AV共包含Scramble、Turbo Code、Interleaver、QAM、FFT、Preamble等元件，其中使用Turbo Code來進行錯誤碼更正其編碼率為1/2，並選擇SOVA演算法來進行解碼，再利用1024 QAM來調變子載波，最後經由3072點快速傅立葉轉換來產生輸出訊號，本論文所提出的3072點 IFFT/FFT架構，可使得IFFT-3072元件節省約38.43%的面積使用量，而FFT-3072元件可節省約29.55%的面積使用量，同步機制使用Preamble來傳遞同步訊號，並透過Timing Recover演算法來檢測是否有封包的傳入。
本論文之HomePlug AV系統架構，使用國家晶片中心提供之TN90GUTM製程設計完成，實現之傳送端與接收端的面積分別為833,430 μm2與1,354,824 μm2，最高資料傳送速率可達139.46Mbps，可滿足高品質數位家庭影音系統之需求，並利用低複雜度與低面積的實作方式，來降低設計電路時所遭遇的困難，且電路架構已通過國家晶片中心Cell-Base Design Flow與Xilinx FPGA雙重驗證，並確保其效能與功能性是正確無誤的。

Power Line Communications(PLC) is one of the main existing wired communications technology. Power Line Communications use the Orthogonal Frequency Division Multiplexing (OFDM) technology to transmit data on power line. Therefore, it has many advantages, such as low-cost wire; there is no need to create a new power line.
This thesis implements the HomePlug AV technology standard to design a power line communication system. The architecture of HomePlug AV system includes Scramble, Turbo Code, Interleaver, QAM, FFT, Preamble, etc. Turbo Code is used to perform error correction and the code rate is 1/2. Soft-Output Viterbi algorithm (SOVA) is used to decode the Turbo Code. QAM-1024 is applied to the modulated subcarrier. Finally, the fast Fourier transform (FFT) generates the transmitted data to the power line. In this thesis, the proposed 3072-point IFFT / FFT architecture that makes the IFFT-3072 save about 38.43% area utilization, and FFT-3072 save about 29.55% area utilization. The Preamble is used to transmit the synchronous signals. The timing recover algorithm will detect whether there is an incoming packet.
The HomePlug AV architecture which uses the Chip Implementation Center TN90GUTM process design is completed. The proposed low complexity and low area use the 833,430 μm2 and 1,354,824 μm2 area in the TX and RX, respectively. The maximum data transfer rate is 139.46 Mbps which can satisfy the High-quality digital home audio system. The circuit architecture has been through the Chip Implementation Center Cell-Base Design Flow and Xilinx FPGA Verification.

第一章 簡介 1
1.1 研究動機 1
1.2 論文架構 2
第二章 通訊系統介紹 3
2.1 單載波與多載波的傳輸方式 3
2.2 正交分頻多工調變方式 5
2.3 HomePlug AV規格介紹 6
第三章 HomePlug AV系統架構規劃 9
3.1 Scrambler / DeScrambler 9
3.2 Turbo Encoder 10
3.3 Turbo Decoder 13
3.4 Interleaver/DeInterleaver 18
3.5 QAM/DeQAM 20
3.6 IFFT/FFT 21
3.7 Preamble / Timing Recover 29
3.8 Cyclic Prefix 31
3.9 系統工作頻率 32
第四章 HomePlug AV系統架構實現 33
4.1 Scrambler / DeScrambler架構實現 33
4.2 Turbo Encoder架構實現 34
4.3 Turbo Decoder架構實現 36
4.4 Interleaver/ DeInterleaver架構實現 42
4.5 QAM-1024/ DeQAM-1024架構實現 44
4.6 IFFT-3072架構實現 46
4.7 FFT-3072架構實現 56
4.8 Preamble架構實現 58
4.9 Timing Recover架構實現 59
4.10 HomePlug AV系統架構整合 61
第五章 HomePlug AV系統驗證及模擬 63
5.1 Scramble/DeScramble驗證及模擬 64
5.2 Turbo Encoder/Turbo Decoder驗證及模擬 65
5.3 Interleaver/DeInterleaver驗證及模擬 66
5.4 QAM/DeQAM驗證及模擬 68
5.5 IFFT/FFT驗證及模擬 69
5.6 Preamble/Timing Recover驗證及模擬 71
5.7 HomePlug AV系統驗證及模擬 73
5.8 HomePlug AV系統實現規格 75
5.9 Xilinx FPGA驗證 76
第六章 結論 78
第七章 參考文獻 79

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