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博碩士論文 etd-0623118-212500 詳細資訊
Title page for etd-0623118-212500
論文名稱
Title
設計與實現一個20MHz/32MHz基於鎖相迴路架構的頻率產生器
Design and implementation of a 20MHz/32MHz PLL frequency Synthesizer in 180nm CMOS
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
78
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2018-07-23
繳交日期
Date of Submission
2018-07-26
關鍵字
Keywords
漏電補償、時脈產生、頻率合成器、可程式除頻器、鎖相迴路
Clock generator, PLL, Pulse Swallow, Synthesizer, Leakage-compensated
統計
Statistics
本論文已被瀏覽 5680 次,被下載 0
The thesis/dissertation has been browsed 5680 times, has been downloaded 0 times.
中文摘要
本論文設計了一個基於鎖相迴路架構的頻率合成器,為一個”可穿戴式生醫感測器積體電路”提供所需要的取樣頻率與系統頻率,並與前述類比前端感測電路整合成一系統單晶片,並經由國家晶片中心所提供的TSMC 180nm CMOS 製程技術來進行電路的模擬與製作。其中本論文所設計的整數型頻率合成器,其除頻倍數可由11位元的計數單元控制,輸出頻率為輸入參考頻率的512~2047倍,輸出可調頻率為10MHz~49.9MHz。為了盡可能降低除頻器的耗電量,採用包含漏電補償的動態邏輯電路實現Pulse Swallow除頻器。此顆頻率合成器量測出的相位雜訊為-96.99dBc/Hz@1MHz,當工作在1.8V且工作頻率在32MHz時功率消耗為291.8uW,總晶片面積為0.31*0.45mm^2。
Abstract
This thesis presents a PLL based frequency synthesizer which is used to generate system clocks and sampling clocks for the front-end ASIC “Integrated ExG, Vibration and Temperature Measurement Front-End for Wearable Sensing” to build a SoC without off-chip clock generators. A proposed frequency synthesizer was designed and implemented in 180nm CMOS technology. Based on integer-N phase-locked-loop architecture, the frequency synthesizer multiplies a reference source by 512 to 2047 times with 11-bit fully programmable divider and operates from 10MHz to 49.9MHz. To minimize the current consumption from divider, a pulse-swallow divider consists of dynamic logic circuit with leakage-compensated logic was implemented. The measured phase noise is -96.99dBc/Hz at 1MHz offset and the power consumption is 291.8uW for 1.8V supply at 32MHz output. The die area is 0.31*0.45mm^2.
目次 Table of Contents
論文審定書 i
論文摘要 ii
ABSTRACT iii
CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES ix
CHAPTER1 INTRODUCTION 1
1.1 Motivation 1
1.2 Organization of thesis 2
CHAPTER2 PHASE LOCKED LOOP FREQUENCY SYNTHESIZERS 3
2.1 The principle of phase-locked loops 3
2.1.1 Typical Charge Pump PLL Loop Analysis 6
2.1.2 Phase Noise Analysis of Charge Pump PLL 12
2.1.3 Loop Filter Analysis 14
2.2 Types of Frequency Synthesizer 17
2.2.1 Integer-N Frequency Synthesizer 17
2.2.2 Fractional-N Frequency Synthesizer 18
2.3 Summary 19
CHAPTER3 DESIGN AND IMPLEMENTATION OF A 20MHZ/32 MHZ PLL SYNTHESIZER IN 180NM CMOS 20
3.1 System Block Diagram 20
3.2 Building Block and Simulation 21
3.2.1 Phase-Frequency Detector 22
3.2.2 Charge Pump Circuit 25
3.2.3 Voltage Control Oscillator 32
3.2.4 Fully Programmable Divider 38
3.2.5 Design of Loop Filter 51
3.3 Summary 53
CHAPTER4 MEASURMENT RESULT 55
4.1 Chip Floor Plan and PCB Design 55
4.2 Environment Setup 56
4.3 Measurement Results 57
4.4 Summary 63
CHAPTER5 CONCLUSIONS AND FUTURE WORK 64
5.1 Conclusions 64
5.2 Future work 64
REFERENCE 66
參考文獻 References
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