本論文的第一部份，提出一新的架構其自我更新週期在DRAM待機模式下會隨溫度動態改變以減少功率消耗。所提出之電路藉由監看因漏電流所造成記憶單元的資料遺失情況來調整更新週期，因而自我更新週期將隨溫度改變而改變，達到省電之目的。

本論文的第二部分，提出兩個運用於NOR-NOR PLA的CMOS快速半波電路。一個附加的1/2VDD電壓源和一個傳輸閘被插入兩個NOR平面之間，用來消除追繞問題和縮短輸出上升延遲和下降延遲時間，提高運算速度。

The first part of this thesis presents a novel design for DRAMs to provide self-refreshing cycles which vary with temperature dynamically to reduce power dissipation in a standby mode. The proposed design monitors the data loss of a memory cell which is resulted from the leakage current, and then adjusts the period of the self-refreshing cycles.

The second part presents two fast half-swing CMOS circuits for NOR-NOR PLA implementation. An additional 1/2VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced.

摘要 i
Abstract ii
第一章 簡介 1
1.1 前言 1
1.2 先前相關文獻探討 2
1.2.1 自我更新功率消耗 2
1.2.2 相關PLA架構 3
1.3 論文目的 3
1.4 論文大綱 4
第二章 具有適應性更新週期的動態隨機存取記憶體模組 5
2.1 簡介 5
2.2 論文製程選擇說明 7
2.3 架構簡介 8
2.3.1 適應性震盪器 8
2.3.2 晶片架構 12
2.3.3 DRAM基本架構 13
2.3.4 DRAM之操作 16
2.3.5 時序控制器 18
2.3.6 感測放大器 21
2.3.7 位址閂鎖器 23
2.3.8 位址選擇器 24
2.3.9 內部位址計數器 24
2.3.10 記憶單元電容佈局架構 24
2.4 模擬結果 25
2.4.1 適應性震盪器模擬 25
2.4.2 晶片模擬 28
2.5 晶片量測結果 33
2.5.1 適應性震盪器更新週期量測 33
2.5.2 晶片DRAM讀寫測試 37
2.5.3 自我更新模式測試 40
2.6 結論 43
第三章 快速半波NOR-NOR PLA架構 45
3.1 簡介 45
3.2 半波快速NOR-NOR PLA設計 47
3.2.1 一般NOR-NOR PLA電路架構 47
3.2.2 半波NOR-NOR PLA電路架構 48
3.2.3 修改型半波Dynamic NOR-NOR PLA電路架構 51
3.3 速度與面積overhead分析 54
3.3.1 速度分析 54
3.3.2 面積overhead分析 54
3.4 模擬分析 55
3.4.1 速度模擬 55
3.4.2 功率消耗模擬 62
3.4.3 修改型半波Dynamic NOR-NOR PLA電路模擬 63
3.5 半波電路架構CLA加法器晶片測試 66
3.6 結論 69
第四章 結論 70
參考文獻 71

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